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publication number S34ML01G1_04g1 revision 17 issue date november 22, 2013 spansion ? slc nand flash memory for embedded spansion ? slc nand flash memory for embedded cover sheet 1 gb, 2 gb, 4 gb densities: 1-bit ecc, x8 and x16 i/o, 3v v cc S34ML01G1, s34m l02g1, s34ml04g1 data sheet notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions. free datasheet http://www.datasheet-pdf.com/
2spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office. free datasheet http://www.datasheet-pdf.com/
this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. dee ms the products to have been in sufficient pro- duction volume such that subsequent versions of this document are not expected to change. however, typographical or specificati on corrections, or modifications to the valid com- binations offered may occur. publication number S34ML01G1_04g1 revision 17 issue date november 22, 2013 distinctive characteristics ? density ? 1 gbit / 2 gbit / 4 gbit ? architecture ? input / output bus width: 8-bits / 16-bits ? page size: ? x8 = 2112 (2048 + 64) bytes; 64 bytes is spare area ? x16 = 1056 (1024 + 32) words; 32 words is spare area ? block size: 64 pages ? x8 = 128k + 4k bytes ? x16 = 64k + 2k words ? plane size: ? 1 gbit / 2 gbit: 1024 blocks per plane x8 = 128m + 4m bytes x16 = 64m + 2m words ? 4 gbit: 2048 blocks per plane x8 = 256m + 8m bytes x16 = 128m + 4m words ?device size: ? 1 gbit: 1 plane per device or 128 mbyte ? 2 gbit: 2 planes per device or 256 mbyte ? 4 gbit: 2 planes per device or 512 mbyte ? nand flash interface ? open nand flash interface (onfi) 1.0 compliant ? address, data and commands multiplexed ? supply voltage ? 3.3v device: vcc = 2.7v ~ 3.6v ? security ? one time programmable (otp) area ? hardware program/erase disabled during power transition ? additional features ? 2 gb and 4 gb parts support multiplane program and erase commands ? supports copy back program ? 2 gb and 4 gb parts support multiplane copy back program ? supports read cache ? electronic signature ? manufacturer id: 01h ? operating temperature ? industrial: -40c to 85c ? automotive: -40c to 105c performance ? page read / program ? random access: 25 s (max) ? sequential access: 25 ns (min) ? program time / multiplane program time: 200 s (typ) ? block erase (S34ML01G1) ? block erase time: 2.0 ms (typ) ? block erase / multiplane erase (s34ml02g1, s34ml04g1) ? block erase time: 3.5 ms (typ) ? reliability ? 100,000 program / erase cycles (typ) (with 1 bit ecc per 528 bytes (x8) or 264 words (x16)) ? 10 year data retention (typ) ? blocks zero and one are valid and will be valid for at least 1000 program-erase cycles with ecc ? package options ? lead free and low halogen ? 48-pin tsop 12 x 20 x 1.2 mm ? 63-ball bga 9 x 11 x 1 mm spansion ? slc nand flash memory for embedded 1 gb, 2 gb, 4 gb densities: 1-bit ecc, x8 and x16 i/o, 3v v cc S34ML01G1, s34m l02g1, s34ml04g1 data sheet free datasheet http://www.datasheet-pdf.com/
4 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5 array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.6.1 S34ML01G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.6.2 s34ml02g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.6.3 s34ml04g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.7 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2. bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1 command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 address input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4 data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.5 write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.6 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3. command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 multiplane program ? s34ml02g1 and s34ml04g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4 page reprogram ? s34ml02g1 and s34ml04g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5 block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.6 multiplane block erase ? s34ml02g1 and s34ml04g1 . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.7 copy back program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.7.1 multiplane copy back program ? s34ml02g1 and s34ml04g1 . . . . . . . . . . . . . . . . . .26 3.7.2 special read for copy back ? s34ml02g1 and s34ml04g1 . . . . . . . . . . . . . . . . . . . .26 3.8 edc operation ? s34ml02g1 and s34ml04g1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.8.1 read edc status register ? s3 4ml02g1 and s34ml04g1 . . . . . . . . . . . . . . . . . . . . .27 3.9 read status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.10 read status enhanced ? s34ml02g1 and s34ml04g1 . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.11 read status register field definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.12 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.13 read cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.14 cache program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.15 multiplane cache program ? s34ml02g1 and s34ml04g1 . . . . . . . . . . . . . . . . . . . . . . . 31 3.16 read id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.17 read id2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.18 read onfi signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.19 read parameter page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.20 one-time programmable (otp) entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4. signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 4.1 data protection and power on / off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2 ready/busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3 write protect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1 valid blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3 ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.6 pin capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 5 data sheet 5.7 program / erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6. timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.1 command latch cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.2 address latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3 data input cycle timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.4 data output cycle timing (cle=l, we#=h, ale=l, wp #=h) . . . . . . . . . . . . . . . . . . . . . . . 45 6.5 data output cycle timing (edo type, cle=l, we#=h, ale=l) . . . . . . . . . . . . . . . . . . . . . 45 6.6 page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.7 page read operation (interrupted by ce#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.8 page read operation timing with ce# don?t care. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.9 page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.10 page program operation timing with ce# don?t care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.11 page program operation with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.12 random data output in a page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.13 multiplane page program operation ? s34ml02g1 and s34ml04g1 . . . . . . . . . . . . . . . . 49 6.14 block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.15 multiplane block erase ? s34ml02g1 and s34ml04g1 . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.16 copy back read with option al data readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.17 copy back program operation with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.18 multiplane copy back program ? s34ml02g1 and s34ml04g1 . . . . . . . . . . . . . . . . . . . . 53 6.19 read status register timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.20 read status enhanced timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.21 reset operation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.22 read cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.23 cache program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.24 multiplane cache program ? s34ml02g1 and s34ml04g1 . . . . . . . . . . . . . . . . . . . . . . . 59 6.25 read id operation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.26 read id2 operation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.27 read onfi signature timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.28 read parameter page timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.29 otp entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.30 power on and data protection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.31 wp# handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7. physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.1 physical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.1.1 48-pin thin small outline package (tsop1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 7.1.2 63-pin ball grid array (bga) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 6 8. system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9. error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.1 system bad block replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.2 bad block management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 free datasheet http://www.datasheet-pdf.com/
6spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet figures figure 1.1 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 1.2 48-pin tsop1 contact x8, x16 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 1.3 63-bga contact, x8 device (balls down, top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 1.4 63-bga contact, x16 device (balls down, top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 1.5 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 1.6 array organization ? x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 1.7 array organization ? x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3.1 page reprogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 3.2 page reprogram with data manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4.1 ready/busy pin electrical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 4.2 wp# low timing requirements during program/erase command sequence . . . . . . . . . . . 39 figure 6.1 command latch cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 6.2 address latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 6.3 input data latch cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 6.4 data output cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 6.5 data output cycle timing (edo). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 6.6 page read operation (read one page) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 figure 6.7 page read operation interrupted by ce# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 6.8 page read operation timing with ce# don?t care. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 6.9 page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 6.10 page program operation timing with ce# don?t care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 6.11 random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 6.12 random data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 6.13 multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 6.14 multiplane page program (onfi 1.0 protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 figure 6.15 block erase operation (erase one block). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 6.16 multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 6.17 multiplane block erase (onfi 1.0 protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 6.18 copy back read with optional data readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 6.19 copy back program with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 6.20 multiplane copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 6.21 multiplane copy back program (onfi 1.0 protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 6.22 status / edc read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 6.23 read status enhanced timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 6.24 reset operation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 6.25 read cache operation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 6.26 ?sequential? read cache timi ng, start (and continua tion) of cache operation . . . . . . . . . 56 figure 6.27 ?random? read cache timing, start (and contin uation) of cache operation . . . . . . . . . . . 57 figure 6.28 read cache timing, end of cache operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 6.29 cache program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 6.30 multiplane cache program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 6.31 multiplane cache program (onfi 1. 0 protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 6.32 read id operation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 6.33 read id2 operation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 6.34 onfi signature timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 6.35 read parameter page timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 6.36 otp entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 6.37 power on and data protection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 6.38 program enabling / disabling through wp# handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 6.39 erase enabling / disabling through wp# handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 7.1 ts/tsr 48 ? 48-lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . 65 figure 7.2 vbm063 ? 63-pin bga, 11 mm x 9 mm package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 8.1 program operation with ce# don't care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 8.2 read operation with ce# don't care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 7 data sheet figure 8.3 page programming within a block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 9.1 bad block replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 9.2 bad block management flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 free datasheet http://www.datasheet-pdf.com/
8 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet tables table 1.1 signal names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 1.2 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 1.3 address cycle map ? 1 gb device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 1.4 address cycle map ? 2 gb device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 1.5 address cycle map ? 4 gb device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 1.6 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3.1 command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 3.2 edc register coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 3.3 page organization in edc units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 3.4 page organization in edc units by address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 3.5 status register coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 3.6 read id for supported configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 3.7 read id bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 3.8 read id byte 3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 3.9 read id byte 4 description ? S34ML01G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 3.10 read id byte 4 description ? s34ml02g1 and s34ml04g1 . . . . . . . . . . . . . . . . . . . . . . . 34 table 3.11 read id byte 5 description ? s34ml02g1 and s34ml04g1 . . . . . . . . . . . . . . . . . . . . . . . 34 table 3.12 parameter page description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.1 valid blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.3 ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 5.5 dc characteristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 5.6 pin capacitance (ta = 25c, f=1.0 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 5.7 program / erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 9.1 block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 9 data sheet 1. general description the spansion S34ML01G1, s34m l02g1, and s34ml04g1 series is offered in 3.3 v cc and v ccq power supply, and with x8 or x16 i/o interfac e. its nand cell provides the most cost-effective solution for the solid state mass storage market. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased . the page size for x8 is (2048 + 64 spare) bytes; for x16 (1024 + 32) words. each block can be programmed and erased up to 10 0,000 cycles with ecc (error correction code) on. to extend the lifetime of nand flash devices, the implementation of an ecc is mandatory. the chip supports ce# don't care function. this functi on allows the direct download of the code from the nand flash memory device by a microcontroller, since the ce# transitions do not stop the read operation. the devices have a read cache feature that improves the read throughput for large files. during cache reading, the devices load the data in a cache register while the previous data is transferred to the i/o buffers to be read. like all other 2-kb page nand flash devices, a progra m operation typically writes 2112 bytes (x8), or 1056 words (x16) in 200 s and an erase operation can typically be performed in 2 ms (S34ML01G1) on a 128-kb block (x8) or 64-kword block (x16). in addition, thanks to multiplane archit ecture, it is possible to program two pages at a time (one per plane) or to erase two blo cks at a time (again, one per plane). the multiplane architecture allows program time to be reduc ed by 40% and erase time to be reduced by 50%. in multiplane operations, data in the page can be read out at 25 ns cycle time per byte. the i/o pins serve as the ports for command and address input as well as data input/output. this interface allows a reduced pin count and easy migration towards different densitie s, without any rearrang ement of t he footprint. commands, data, and addresses are asynchronously in troduced using ce#, we#, ale, and cle control pins. the on-chip program/erase controller automates all read, program, and erase functions including pulse repetition, where required, and internal verification and margining of data. a wp# pin is available to provide hardware protection against pr ogram and erase operations. the output pin r/b# (open drain buffer) signals the status of the device durin g each operation. it identifies if the program/erase/read controller is currently active. the use of an open-drain ou tput allows the ready/busy pins from several memories to connect to a single pull-up re sistor. in a system with multiple memories the r/b# pins can be connected all toget her to provide a global status signal. the reprogram function allows the optimization of defective block management ? when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. the copy back operation automat ically executes embedded error detection operation: 1-bit error out of every 528 byte s (x8) or 256 words (x16) c an be detected. with this feature it is no longer necessary to use an extern al mechanism to detect copy back operation errors. multiplane copy back is also supported. data read out a fter copy back read (both for single and multiplane cases) is allowed. in addition, cache program and multiplane cache prog ram operations improve the programing throughput by programing data using the cache register. the devices provide two innovative features: page reprogram and multiplane page reprogram. the page reprogram re-programs one page. normally, this operation is performed after a failed page program operation. similarly, the multiplane page reprogram re -programs two pages in parallel, one per plane. the first page must be in the first plane while the second page must be in the second plane. the multiplane page reprogram operation is performed after a failed multip lane page program operatio n. the page reprogram and multiplane page reprogram guarantee improved per formance, since data insertion can be omitted during re-program operations. note : the S34ML01G1 device does not support edc. free datasheet http://www.datasheet-pdf.com/
10 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet the devices come with an otp (one time programmabl e) area, which is a restricted access area where sensitive data/code can be st ored permanently. this security feature is subject to an nda (non-disclosure agreement) and is, therefore, not described in the da ta sheet. for more details, contact your nearest spansion sales office. 1.1 logic diagram figure 1.1 logic diagram device density (bits) number of planes number of blocks per plane edc support main spare S34ML01G1 128m x 8 64m x 16 4m x 8 2m x 16 1 1024 no s34ml02g1 256m x 8 128m x 16 8m x 8 4m x 16 2 1024 yes s34ml04g1 512m x 8 256m x 16 16m x 8 8m x 16 2 2048 yes table 1.1 signal names i/o7 - i/o0 (x8) data input / outputs i/o8 - i/o15 (x16) cle command latch enable ale address latch enable ce# chip enable re# read enable we# write enable wp# write protect r/b# read/busy vcc power supply vss ground nc not connected vcc v ss wp# cle ale re# we# ce# i/o0 ~ i/o7 r/b# free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 11 data sheet 1.2 connection diagram figure 1.2 48-pin tsop1 contact x8, x16 devices note: 1. these pins should be connected to power supply or ground (as des ignated) following the onfi specification, however they might not be bonded internally. figure 1.3 63-bga contact, x8 device (balls down, top view) note: 1. these pins should be connected to power supply or ground (as des ignated) following the onfi specification, however they might not be bonded internally. nc nc nc nc nc nc r/b# re# ce# nc nc vcc v ss nc nc cle ale we# wp# nc nc nc nc nc v ss nc nc nc i/o7 i/o6 i/o5 i/o4 nc vcc nc vcc v ss nc vcc nc i/o 3 i/o2 i/o1 i/o0 nc nc nc v ss 12 1 3 3 7 3 6 25 4 8 1 24 nand fl as h t s op1 x 8 x 8 nc nc nc nc nc nc r/b# re# ce# nc nc vcc v ss nc nc cle ale we# wp# nc nc nc nc nc x16 x16 v ss i/o15 i/o14 i/o1 3 i/o7 i/o6 i/o5 i/o4 i/o12 vcc nc vcc v ss nc vcc i/011 i/o 3 i/o2 i/o1 i/o0 i/o10 i/o9 i/o 8 v ss (1) (1) (1) (1) f3 f4 f5 f6 f7 f8 e3 e4 e5 e6 e7 e8 d3 d4 d5 d6 d7 d8 c3 c4 c5 c6 c7 c8 rb# we# ce# vss ale wp# nc nc nc cle re# vcc (1) nc nc nc nc nc nc g3 g4 g5 g6 g7 g8 nc vss (1) nc nc nc nc h3 h4 h5 h6 h7 h8 v cc nc nc nc i/o0 nc b9 a9 nc nc a2 nc nc nc nc nc vcc (1) nc b10 a10 nc nc b1 a1 nc nc j3 j4 j5 j6 j7 j8 i/o7 i/o5 v cc nc i/o1 nc k3 k4 k5 k6 k7 k8 v ss i/o6 i/o4 i/o3 i/o2 v ss l9 nc l2 nc l10 nc l1 nc m9 nc m2 nc m10 nc m1 nc free datasheet http://www.datasheet-pdf.com/
12 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet figure 1.4 63-bga contact, x16 device (balls down, top view) 1.3 pin description notes: 1. a 0.1 f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations. 2. an internal voltage detector disables all functions whenever v cc is below 1.8v to protect the device from any involuntary program/erase during power transitions. f3 f4 f5 f6 f7 f8 e3 e4 e5 e6 e7 e8 d3 d4 d5 d6 d7 d8 c3 c4 c5 c6 c7 c8 rb# we# ce# vss ale wp# nc nc nc cle re# vcc nc nc nc nc nc nc g3 g4 g5 g6 g7 g8 nc vss nc nc nc nc h3 h4 h5 h6 h7 h8 v cc i/o14 i/o12 i/o10 i/o0 i/o8 b9 a9 nc nc a2 nc nc i/o15 i/o13 nc vcc nc b10 a10 nc nc b1 a1 nc nc j3 j4 j5 j6 j7 j8 i/o7 i/o5 v cc i/o11 i/o1 i/o9 k3 k4 k5 k6 k7 k8 v ss i/o6 i/o4 i/o3 i/o2 v ss l9 nc l2 nc l10 nc l1 nc m9 nc m2 nc m10 nc m1 nc table 1.2 pin description pin name description i/o0 - i/o7 (x8) inputs/outputs . the i/o pins are used for command input, addr ess input, data input, and data output. the i/o pins float to high-z when the device is deselected or the outputs are disabled. i/o8 - i/o15 (x16) cle command latch enable. this input activates the latching of the i/o inputs inside the command register on the rising edge of write enable (we#). ale address latch enable. this input activates the latching of the i/o in puts inside the address register on the rising edge of write enable (we#). ce# chip enable. this input controls the selection of the device. when the device is not busy ce# low selects the memory. we# write enable. this input latches command, address and data. the i/o inputs are latched on the rising edge of we#. re# read enable. the re# input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid t rea after the falling edge of re# which also increments the internal column address counter by one. wp# write protect. the wp# pin, when low, provides hardware protection against undesired data modification (program / erase). r/b# ready busy . the ready/busy output is an open drain pin that signals the state of the memory. vcc supply voltage . the v cc supplies the power for all the operations (read, program, erase). an internal lock circuit prevents the insertion of commands when v cc is less than v lko . vss ground. nc not connected. free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 13 data sheet 1.4 block diagram figure 1.5 functional block diagram addre ss regi s ter/ co u nter controller comm a nd interf a ce logic comm a nd regi s ter d a t a regi s ter re# i/o b u ffer y decoder page b u ffer x d e c o d e r nand fl as h memory arr a y wp# ce# we# cle ale i/o0 ~ i/o7 (x 8 ) i/o0 ~ i/o15 (x16) 1024 m b it + 3 2 m b it (1 g b device) progr a m er as e hv gener a tion 204 8 m b it + 64 m b it (2 g b device) 4096 m b it + 12 8 m b it (4 g b device) free datasheet http://www.datasheet-pdf.com/
14 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 1.5 array organization figure 1.6 array organization ? x8 figure 1.7 array organization ? x16 pl a ne( s ) 204 8 b yte s 64 b yte s i/o [7:0] 1 p a ge = (2k + 64) b yte s 1 block = (2k + 64) b yte s x 64 p a ge s = (12 8 k + 4k) b yte s 1 pl a ne = (12 8 k + 4k) b yte s x 1024 block s p a ge b u ffer 1024 block s per pl a ne 1022 102 3 1 0 2 arr a y org a niz a tion (x 8 ) for 1 g b a nd 2 g b device s there a re 1024 block s per pl a ne for 4 g b device there a re 204 8 block s per pl a ne note : 2 g b a nd 4 g b device s h a ve two pl a ne s pl a ne( s ) 1024 word s i/o0 ~ i/o15 1 p a ge = (1k + 3 2) word s 1 block = (1k + 3 2) word s x 64 p a ge s = (64k + 2k) word s 1 pl a ne = (64k + 2k) word s x 1024 block s p a ge b u ffer 1024 block s per pl a ne 1022 102 3 1 0 2 arr a y org a niz a tion (x16) for 1 g b a nd 2 g b device s there a re 1024 block s per pl a ne for 4 g b device there a re 204 8 block s per pl a ne note : 2 g b a nd 4 g b device s h a ve two pl a ne s 3 2 word s free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 15 data sheet 1.6 addressing 1.6.1 S34ML01G1 notes: 1. cax = column address bit. 2. pax = page address bit. 3. bax = block address bit. 4. block address concatenated with page address = actu al page address, also known as the row address. 5. i/o[15:8] are not used during the add ressing sequence and should be driven low. for the x8 address bits, the following rules apply: ? a0 - a11: column address in the page ? a12 - a17: page address in the block ? a18 - a27: block address for the x16 address bits, the following rules apply: ? a0 - a10: column address in the page ? a11 - a16: page address in the block ? a17 - a26: block address table 1.3 address cycle map ? 1 gb device bus cycle i/o [15:8] (5) i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 x8 1st / col. add. 1 ? a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 ? a8 (ca8) a9 (ca9) a10 (ca10) a11 (ca11) low low low low 3rd / row add. 1 ? a12 (pa0) a13 (pa1) a14 (pa2) a15 (pa3) a16 (pa4) a17 (pa5) a18 (ba0) a19 (ba1) 4th / row add. 2 ? a20 (ba2) a21 (ba3) a22 (ba4) a23 (ba5) a24 (ba6) a25 (ba7) a26 (ba8) a27 (ba9) x16 1st / col. add. 1 low a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 low a8 (ca8) a9 (ca9) a10 (ca10) low low low low low 3rd / row add. 1 low a11 (pa0) a12 (pa1) a13 (pa2) a14 (pa3) a15 (pa4) a16 (pa5) a17 (ba0) a18 (ba1) 4th / row add. 2 low a19 (ba2) a20 (ba3) a21 (ba4) a22 (ba5) a23 (ba6) a24 (ba7) a25 (ba8) a26 (ba9) free datasheet http://www.datasheet-pdf.com/
16 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 1.6.2 s34ml02g1 notes: 1. cax = column address bit. 2. pax = page address bit. 3. pla0 = plane address bit zero. 4. bax = block address bit. 5. block address concatenated with page address and plane addre ss = actual page address, also known as the row address. 6. i/o[15:8] are not used during the add ressing sequence and should be driven low. for the x8 address bits, the following rules apply: ? a0 - a11: column address in the page ? a12 - a17: page address in the block ? a18: plane address (for multiplane operations) / block address (for normal operations) ? a19 - a28: block address for the x16 address bits, the following rules apply: ? a0 - a10: column address in the page ? a11 - a16: page address in the block ? a17: plane address (for multiplane operations) / block address (for normal operations) ? a18 - a27: block address table 1.4 address cycle map ? 2 gb device bus cycle i/o [15:8] (6) i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 x8 1st / col. add. 1 ? a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 ? a8 (ca8) a9 (ca9) a10 (ca10) a11 (ca11) low low low low 3rd / row add. 1 ? a12 (pa0) a13 (pa1) a14 (pa2) a15 (pa3) a16 (pa4) a17 (pa5) a18 (pla0) a19 (ba0) 4th / row add. 2 ? a20 (ba1) a21 (ba2) a22 (ba3) a23 (ba4) a24 (ba5) a25 (ba6) a26 (ba7) a27 (ba8) 5th / row add. 3 ? a28 (ba9) low low low low low low low x16 1st / col. add. 1 low a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 low a8 (ca8) a9 (ca9) a10 (ca10) low low low low low 3rd / row add. 1 low a11 (pa0) a12 (pa1) a13 (pa2) a14 (pa3) a15 (pa4) a16 (pa5) a17 (pla0) a18 (ba0) 4th / row add. 2 low a19 (ba1) a20 (ba2) a21 (ba3) a22 (ba4) a23 (ba5) a24 (ba6) a25 (ba7) a26 (ba8) 5th / row add. 3 low a27 (ba9) low low low low low low low free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 17 data sheet 1.6.3 s34ml04g1 notes: 1. cax = column address bit. 2. pax = page address bit. 3. pla0 = plane address bit zero. 4. bax = block address bit. 5. block address concatenated with page address and plane addre ss = actual page address, also known as the row address. 6. i/o[15:8] are not used during the add ressing sequence and should be driven low. for the x8 address bits, the following rules apply: ? a0 - a11: column address in the page ? a12 - a17: page address in the block ? a18: plane address (for multiplane operations) / block address (for normal operations) ? a19 - a29: block address for the x16 address bits, the following rules apply: ? a0 - a10: column address in the page ? a11 - a16: page address in the block ? a17: plane address (for multiplane operations) / block address (for normal operations) ? a18 - a28: block address table 1.5 address cycle map ? 4 gb device bus cycle i/o [15:8] (6) i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 x8 1st / col. add. 1 ? a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 ? a8 (ca8) a9 (ca9) a10 (ca10) a11 (ca11) low low low low 3rd / row add. 1 ? a12 (pa0) a13 (pa1) a14 (pa2) a15 (pa3) a16 (pa4) a17 (pa5) a18 (pla0) a19 (ba0) 4th / row add. 2 ? a20 (ba1) a21 (ba2) a22 (ba3) a23 (ba4) a24 (ba5) a25 (ba6) a26 (ba7) a27 (ba8) 5th / row add. 3 ? a28 (ba9) a29 (ba10) low low low low low low x16 1st / col. add. 1 low a0 (ca0) a1 (ca1) a2 (ca2) a3 (ca3) a4 (ca4) a5 (ca5) a6 (ca6) a7 (ca7) 2nd / col. add. 2 low a8 (ca8) a9 (ca9) a10 (ca10) low low low low low 3rd / row add. 1 low a11 (pa0) a12 (pa1) a13 (pa2) a14 (pa3) a15 (pa4) a16 (pa5) a17 (pla0) a18 (ba0) 4th / row add. 2 low a19 (ba1) a20 (ba2) a21 (ba3) a22 (ba4) a23 (ba5) a24 (ba6) a25 (ba7) a26 (ba8) 5th / row add. 3 low a27 (ba9) a28 (ba10) low low low low low low free datasheet http://www.datasheet-pdf.com/
18 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 1.7 mode selection notes: 1. x can be v il or v ih . high= logic level high. low = logic level low. 2. wp# should be biased to cmos high or cmos low for stand-by mode. 3. during busy time in read, re# must be held high to prevent unintended data out. 2. bus operation there are six standard bus operations that control the device: command input, address i nput, data input, data output, write prot ect, and standby. (see table 1.6 .) typically glitches less than 5 ns on chip enable, writ e enable, and read enable are ignored by the memory and do not affect bus operations. 2.1 command input the command input bus operation is used to give a command to the memory device. commands are accepted with chip enable low, command latch enable high, address latch enable low, and read enable high and latched on the rising edge of write enable. mo reover, for commands that start a modify operation (program/erase) the write protect pin must be high. see figure 6.1 on page 43 and table 5.4 on page 41 for details of the timing requirements. command codes are always applied on i/o7:0 regardless of the bus configuration (x8 or x16). 2.2 address input the address input bus operation allows the inserti on of the memory address. for the s34ml02g1 and s34ml04g1 devices, five write cycles are needed to in put the addresses. for the S34ML01G1, four write cycles are needed to input the addresses. if nece ssary, a 5th dummy address cycle can be issued to S34ML01G1, which will be ignored by the nand devi ce without causing problems. addresses are accepted with chip enable low, address latch enable high, co mmand latch enable low, and read enable high and latched on the rising edge of write enable. moreover, for commands that start a modify operation (program/ erase) the write protect pin must be high. see figure 6.2 on page 44 and table 5.4 on page 41 for details of the timing requirements. addresses are always applied on i/o7:0 regardless of the bus configuration (x8 or x16). refer to table 1.3 through table 1.5 on page 17 for more detailed information. table 1.6 mode selection mode cle ale ce# we# re# wp# read mode command input high low low rising high x address input low high low rising high x program or erase mode command input high low low rising high high address input low high low rising high high data input low low low rising high high data output (on going) low low low high falling x data output (suspended) x x x high high x busy time in read x x x high high (3) x busy time in program x x x x x high busy time in erase x x x x x high write protect x x x x x low stand by x x high x x 0v / v cc (2) free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 19 data sheet 2.3 data input the data input bus operation allows the data to be program med to be sent to the device. the data insertion is serial and timed by the write enable cycles. data is accepted only with chip enable low, address latch enable low, command latch enable low, read enable high, and write protect high and latched on the rising edge of write enable. see figure 6.3 on page 44 and table 5.4 on page 41 for details of the timing requirements. 2.4 data output the data output bus operation allows data to be read from the memory array and to check the status register content, the edc register content, and the id data. data can be serially shifted out by toggling the read enable pin with chip enable low, write enable high, address latch enable low, and command latch enable low. see figure 6.4 on page 45 and table 5.4 on page 41 for details of the timings requirements. 2.5 write protect the hardware write protection is activated when the wr ite protect pin is low. in this condition, modify operations do not start and the content of the memory is not altered. the write prot ect pin is not latched by write enable to ensure the pr otection even during power up. 2.6 standby in standby, the device is deselected, outputs are disabled, and power consumption is reduced. free datasheet http://www.datasheet-pdf.com/
20 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 3. command set table 3.1 command set command 1st cycle 2nd cycle 3rd cycle 4th cycle acceptable command during busy supported on S34ML01G1 page read 00h 30h no yes page program 80h 10h no yes random data input 85h no yes random data output 05h e0h no yes multiplane program 80h 11h 81h 10h no no onfi multiplane program 80h 11h 80h 10h no no page reprogram 8bh 10h no no multiplane page reprogram 8bh 11h 8bh 10h no no block erase 60h d0h no yes multiplane block erase 60h 60h d0h no no onfi multiplane block erase 60h d1h 60h d0h no no copy back read 00h 35h no yes copy back program 85h 10h no yes multiplane copy back program 85h 11h 81h 10h no no onfi multiplane copy back program 85h 11h 85h 10h no no special read for copy back 00h 36h no no read edc status register 7bh yes no read status register 70h yes yes read status enhanced 78h yes no reset ffh yes yes read cache 31h no yes read cache enhanced 00h 31h no no read cache end 3fh no yes cache program (end) 80h 10h no yes cache program (start) / (continue) 80h 15h no yes multiplane cache program (start/continue) 80h 11h 81h 15h no no onfi multiplane cache program (start/continue) 80h 11h 80h 15h no no multiplane cache program (end) 80h 11h 81h 10h no no onfi multiplane cache program (end) 80h 11h 80h 10h no no read id 90h no yes read id2 30h-65h-00h 30h no yes read onfi signature 90h no yes read parameter page ech no yes one-time programmable (otp) area entry 29h-17h-04h-19h no yes free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 21 data sheet 3.1 page read page read is initiated by writing 00h and 30h to the co mmand register along with five address cycles (four or five cycles for S34ML01G1). two types of operations are available: random read and serial page read. random read mode is enabled when the page address is changed. all data within the selected page are transferred to the data r egisters. the system controlle r may detect the completion of this data transfer (t r ) by analyzing the output of the r/b pin. once the data in a page is loaded into the data registers, they may be read out in 25 ns cycle time by sequentially pulsing re #. the repetitive high to low transitions of the re# signal makes the device output the data, starting fr om the selected column address up to the last column address. the device may output random data in a page instead of the sequential data by writing random data output command. the column address of next data, which is going to be out, may be changed to the address that follows random data output command. random data output can be performed as many times as needed. after power up, the device is in read mode, so 00h comm and cycle is not necessary to start a read operation. any operation other than read or random data output causes the device to exit read mode. see figure 6.6 on page 46 and figure 6.12 on page 49 as references. 3.2 page program a page program cycle consists of a serial data loading period in which up to 2112 bytes (x8) or 1056 words (x16) of data may be loaded into the data register, fo llowed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the se rial data input command (80h), followed by the five cycle address inputs (four cycles for S34ML01G1) and then serial data. the words other than those to be programmed do not need to be loaded. the device suppo rts random data input within a page. the column address of next data, which will be entered, may be chan ged to the address that follows the random data input command (85h). random data input ma y be performed as many times as needed. the page program confirm command (10h) initiates th e programming process. the internal write state controller automatically executes the algorithms and controls timings necessary for program and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status regi ster commands (70h or 78h) may be issued to read the status register. the system cont roller can detect the co mpletion of a program cycle by monitoring the r/b# output, or the status bit (i/o6) of the status register. only the read status commands (70h or 78h) or reset command are valid while programming is in progr ess. when the page program is complete, the write status bit (i/o0) may be checked. the internal write veri fy detects only errors for 1? s that are not successfully programmed to 0?s. the command register remain s in read status command mode until another valid command is written to the command register. figure 6.9 on page 47 and figure 6.11 on page 48 detail the sequence. the device is programmable by page, but it also allo ws multiple partial page programming of a word or consecutive bytes up to 2112 bytes (x8) or 1056 words (x16) in a single page program cycle. the number of consecutive partial page programming operations (nop ) within the same page must not exceed the number indicated in table 5.7 on page 43 . pages may be programmed in any order within a block. users who use ?edc check? (for s34ml02g1 and s34ml04g 1 only) in copy back must comply with some limitations related to data handling during one page program sequence. refer to section 3.8 on page 26 for details. if a page program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted page is not used for furt her reading or programming operations until the next uninterrupted block erase is complete. free datasheet http://www.datasheet-pdf.com/
22 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 3.3 multiplane program ? s34ml02g1 and s34ml04g1 the s34ml02g1 and s34ml04g1 devices support multipl ane program, making it possible to program two pages in parallel, one page per plane. a multiplane program cycle consists of a double serial data loading period in which up to 4224 bytes (x8) or 2112 words (x16) of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins with inputting the serial data input command (80h), followed by the five cycle address inputs and serial data for the 1st page. the address for this page must be in the 1st plane (pla0 = 0). the device supports random data input exactly the same as in the case of pag e program operation. the dummy page program confirm command (11h) stops 1st page data input and the device becomes busy for a short time (t dbsy ). once it has become ready again, the ?81h? command must be issued, followed by 2nd page address (5 cycles) and its serial data input. the address for this page must be in the 2nd plane (pla0 = 1). the program confirm command (10h) starts parallel programming of both pages. figure 6.13 on page 49 describes the sequences using the legacy protocol. in this case, the block address bits for the first plane are all zero and the second address issued selects the block for both planes. figure 6.14 on page 50 describes the sequences using the onfi pr otocol. for both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select the plane. the user can check operation status by monitoring r/b# pin or reading the status register (command 70h or 78h). the read status register command is also available during dummy busy time (t dbsy ). in case of failure in either page program, the fail bit of the status register will be set. refer to section 3.9 on page 28 for further info. the number of consecutive partial page programming operations (nop ) within the same page must not exceed the number indicated in table 5.7 on page 43 . pages may be programmed in any order within a block. if a multiplane program operation is interrupted by hard ware reset, power failure or other means, the host must ensure that the interrupted pages are not used fo r further reading or progra mming operations until the next uninterrupted block erases are co mplete for the applicable blocks. free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 23 data sheet 3.4 page reprogram ? s3 4ml02g1 and s34ml04g1 page program may result in a fail, which can be detected by read status register. in this event, the host may call page reprogram. this command allows the reprog ramming of the same pattern of the last (failed) page into another memory location. the command sequen ce initiates with reprogram setup (8bh), followed by the five cycle address inputs of the target page. if th e target pattern for the destination page is not changed compared to the last page, the program confirm can be issued (10h) without any data input cycle, as described in figure 3.1 . figure 3.1 page reprogram on the other hand, if the pa ttern bound for the target page is different from that of the pr evious page, data in cycles can be issued before program confirm ?10h?, as described in figure 3.2 . figure 3.2 page reprogram with data manipulation s r[6] i/ox cycle type a s defined for p a ge progr a m a a c1 i/ox s r[6] cycle type cmd addr addr addr 00h c2 r1 r 3 p a ge n din din din din cmd d0 d1 . . . dn 10h cmd do u t 70h e1 fail ! p a ge m cmd 10h tadl twb tprog twb tprog addr r2 addr cmd addr addr addr addr addr 8 bh c1 c2 r1 r 3 r2 c1 iox s r[6] s r[6] cycle type i/ox cycle type a s defined for p a ge progr a m a a cmd addr addr addr addr 8 0h c2 r1 r 3 p a ge n din din din din cmd d0 d1 . . . dn 10h cmd addr addr addr addr 8 bh c1 c2 r1 r 3 fail ! p a ge m cmd 10h tadl twb tprog twb tprog cmd do u t 70h e1 din din din din d0 d1 . . . dn tadl addr r2 addr r2 free datasheet http://www.datasheet-pdf.com/
24 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet the device supports random data input within a p age. the column address of next data, which will be entered, may be changed to the address which follows the random data input command (85h). random data input may be operated multiple times regardless of how many times it is done in a page. the program confirm command (10h) initiates the re -programming process. the internal write state controller automatically executes the algorithms and controls timings necessary for program and verify, thereby freeing the system co ntroller for other tasks. once the program process starts, the read status register command may be issued to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/b# out put, or the status bit (i/o6) of the status register. only the read status command and reset command are va lid when programming is in progress. when the page program is complete, the write st atus bit (i/o0) may be checked. the internal write verify detects only errors for 1?s that are not successfully programmed to 0?s. the command register remains in read status command mode until another valid command is written to the command register. the page reprogram must be issued in the same plane as the page program that failed. in order to program the data to a different plane, use the page program o peration instead. the multiplane page reprogram can re-program two pages in parallel, one per plane. t he multiplane page reprogram operation is performed after a failed multiplane page program operation. the command sequence is very similar to figure 6.13 on page 49 , except that it requires the page reprogram command (8bh) instead of 80h and 81h. if a page reprogram operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted page is not used for furt her reading or programming operations until the next uninterrupted block erase is complete. 3.5 block erase the block erase operation is done on a block basis. bl ock address loading is accomplished in three cycles (two cycles for S34ML01G1) initiat ed by an erase setup command (60h). only the block address bits are valid while the page address bits are ignored. the erase confirm command (d0h) following the block addr ess loading initiates the internal erasing process. this two-step sequence of setup followed by the exec ution command ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we# after the erase confirm comma nd input, the internal write controller handles erase and erase verify. once the erase process starts, the read status register commands (70h or 78h) may be issued to read the status register. the system controller can detect the completion of an er ase by monitoring the r/b# output, or the status bit (i/o6) of the status register. only the read status commands (70h or 78h) and reset command are valid while erasing is in progress. when the erase operati on is completed, the write status bit (i/o0) may be checked. figure 6.15 on page 50 details the sequence. if a block erase operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted block is erased under c ontinuous power conditions before that block can be trusted for further programming and reading operations. free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 25 data sheet 3.6 multiplane block erase ? s34ml02g1 and s34ml04g1 multiplane block erase allows the erase of two blocks in parallel, one block per memory plane. the block erase setup command (60h) must be repeated two times, followed by 1st and 2nd block address respectively (3 cycles each). as for block erase, d0h command makes embedded operation start. in this case, multiplane erase does not need any dummy busy time between 1st and 2nd block insertion. see table 5.7 on page 43 for performance information. for the multiplane block erase operation, the address of the first block must be within the first plane (pla0 = 0) and the address of the second block in the second plane (pla0 = 1). see figure 6.16 on page 51 for a description of the legacy protocol . in this case, the block address bits for the first plane are all zero and the second address issued selects the block for both planes. figure 6.17 on page 51 describes the sequences using the onfi protocol. for both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select the plane. the user can check operation status by monitoring r/b# pin or reading the status register (command 70h or 78h). the read status register command is also available during dummy busy time (t dbsy ). in case of failure in either erase, the fail bit of t he status register will be set. refer to section 3.9 on page 28 for further information. if a multiplane block erase operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted blocks are erased under continuous power conditions before those blocks can be trusted for further progr amming and reading operations. 3.7 copy back program the copy back feature is intended to quickly and effici ently rewrite data stored in one page without utilizing an external memory. since the time-con suming cycles of serial access an d re-loading cycles are removed, the system performance is greatly improved. the benefit is es pecially obvious when a portion of a block needs to be updated and the rest of the block also needs to be copied to the newly assigned free block. the operation for performing a copy back is a sequential execution of page-read (without mandatory serial access) and copy back program with the address of destination page. a read operation with the ?35h? command and the address of the source page moves the whole page of data into the internal data register. as soon as the device returns to the ready state, optional da ta read-out is allowed by toggling re# (see figure 6.18 on page 52 ), or the copy back program command (85h) with the address cycles of the destination page may be written. the program confirm command (10h) is required to actually begin programming. the source and the destination pages in the copy ba ck program sequence must belong to the same device plane (same pla0 for s34ml02g1 and s34ml04g1). copy back read and copy back program for a given plane must be between odd address pages or between even address pages for the device to meet the program time (t prog ) specification. copy back program may not meet this specificat ion when copying from an odd address page (source page) to an even address page (target page) or from an even address page (source page) to an odd address page (target page). the data input cycle for modifying a port ion or multiple distin ct portions of the source page is allowed as shown in figure 6.19 on page 52 . as noted in section 1. on page 9 the device may include an automatic edc (for s34ml02g1 and s34ml04g1) check during the copy back operation, to detect single bit errors in edc units contained within the source page. more details on edc operation and limitations related to data input handling during one copy back program sequence are available in section 3.8 on page 26 . if a copy back program operation is interrupted by ha rdware reset, power failure or other means, the host must ensure that the interrupted page is not used for further reading or programming operations until the next uninterrupted block erase is complete. free datasheet http://www.datasheet-pdf.com/
26 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 3.7.1 multiplane copy back progr am ? s34ml02g1 and s34ml04g1 the device supports multiplane copy back program with exactly the same sequenc e and limitations as the page program. multiplane copy back program must be preceded by two single page copy back read command sequences (1st page must be read from the 1st plane and 2nd page from the 2nd plane). multiplane copy back cannot cross plane boundaries ? the contents of the source page of one device plane can be copied only to a destination page of the same plane. edc check is available also for multiplane copy back program only for s34ml02g1 and s34ml04g1. when ?edc check? is used in copy ba ck, it must comply with some limitat ions related to data handling during one multiplane copy back program sequence. please refer to section 3.8 on page 26 for details on edc operation. the multiplane copy back program sequence represented in figure 6.20 on page 53 shows the legacy protocol. in this case, the block address bits for the first plane are all zero and the second address issued selects the block for both planes. figure 6.21 on page 54 describes the sequence using the onfi protocol. for both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select the plane. if a multiplane copy back program operation is interrup ted by hardware reset, power failure or other means, the host must ensure that the interrupt ed pages are not used for further reading or programming operations until the next uninterrupted block eras es are complete for the applicable blocks. 3.7.2 special read for copy back ? s34ml02g1 and s34ml04g1 the s34ml02g1 and s34ml04g1 devices support special read for copy back. if copy back read (described in section 3.7 and section 3.7.1 on page 26 ) is triggered with confirm command ?36h? instead ?35h?, copy back read from target page(s) will be executed with an increased internal (v pass ) voltage. this special feature is used in order to minimize t he number of read errors due to over-program or read disturb ? it shall be used only if ecc read errors have occurred in the source page using page read or copy back read sequences. excluding the copy back read confirm command, all other features described in section 3.7 and section 3.7.1 for standard copy back remain valid (including the figures referred to in those sections). 3.8 edc operation ? s34ml02g1 and s34ml04g1 error detection code check is a feature that can be us ed during the copy back operation (both single and multiplane) to detect single bit errors occurring in the source page(s). note : the S34ML01G1 device does not support edc. ? edc check allows detection of up to 1 single bit error every 528 bytes, where each 528 byte group is composed of 512 bytes of main array and 16 bytes of spare area (see table 3.3 and table 3.4 on page 28 ). the described 528-byte area is called an ?edc unit.? ? in the x16 device, edc allows detection of up to 1 single bit error every 264 words, where each 264 word group is composed by 256 words of main array and 8 words of spare area see table 3.3 and table 3.4 on page 28 ). the described 264-word area is called ? edc unit. ? edc results can be checked through a specific read ed c register command, available only after issuing a copy back program or a multiplane copy back program. the edc register can be queried during the copy back program busy time (t prog ). for the ?edc check? feature to operate correctly, specific conditions on data input handling apply for program operations. for the case of page program, multiplane page progra m, page reprogram, multiplane page reprogram, cache program, and multiplane cache program operations: ? in section 3.2 on page 21 it was explained that a number of consecutive partial program operations (nop) is allowed within the same page. in case this feature is used, the number of partial program operations occurring in the same edc unit must not exceed 1. in other words, page program operations must be performed on the whole page, or on whole edc unit at a time. ? ?random data input? in a given edc unit can be executed several times during one page program sequence, but data cannot be written to any column address more than once before the program is initiated. free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 27 data sheet for the case of copy back program or multiplane copy back program operations: ? if random data input is applied in a given edc unit, the entire edc unit must be wr itten to the page buffer. in other words, the edc check is possible only if the whole edc unit is modified during one copy back program sequence. ? ?random data input? in a given edc unit can be executed several times during one copy back program sequence, but data insertion in each column address of the edc unit must not exceed 1. if you use copy back without edc check, none of the limit ations described above apply. after a copy back program operation, the host can use read edc status register to check the status of both the program operation and the copy back read. if the edc was valid and an error was reported in the edc (see table 3.2 on page 27 ), the host may perform special read for copy back on the source page and attempt the copy back program again. if this also fails, the host can execute a page read operation in order to correct a single bit error with external ecc software or hardware. 3.8.1 read edc stat us register ? s3 4ml02g1 and s34ml04g1 this operation is available only after issuing a copy ba ck program and it allows the detection of errors during copy back read. in the case of mult iplane copy back, it is not possible to know which of the two read operations caused the error. after writing the read edc status register command (7bh) to the command register, a read cycle outputs the content of the edc register to the i/o pins on the falling edge of ce# or re#, whichever occurs last. the operation is the same as the read status register command. refer to table 3.2 for specific edc register definitions: table 3.2 edc register coding id copy back program coding 0 pass / fail pass: 0; fail: 1 1 edc status no error: 0; error: 1 2 edc validity invalid: 0; valid: 1 3na ? 4na ? 5 ready / busy busy: 0; ready: 1 6 ready / busy busy: 0; ready: 1 7 write protect protected: 0; not protected: 1 table 3.3 page organization in edc units main field (2048 byte) spare field (64 byte) ?a? area (1st sector) ?b? area (2nd sector) ?c? area (3rd sector) ?d? area (4th sector) ?e? area (1st sector) ?f? area (2nd sector) ?g? area (3rd sector) ?h? area (4th sector) x8 512 byte 512 byte 512 byte 512 byte 16 byte 16 byte 16 byte 16 byte x16 256 words 256 words 256 words 256 words 8 words 8 words 8 words 8 words free datasheet http://www.datasheet-pdf.com/
28 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 3.9 read status register the status register is used to retrieve the status value for the last operation issued. after writing 70h command to the command register, a read cycle outputs the content of the stat us register to the i/o pins on the falling edge of ce# or re#, whichever occurs last. this two-line control allows the system to poll the progress of each device in multiple memory connection s even when r/b# pins are common-wired. refer to section 3.5 on page 29 for specific status register definition, and to figure 6.22 on page 54 for timings. if the read status register command is issued during multiplane ope rations then status register polling will return the combined status value related to the outcome of the operation in the two planes according to the following table: in other words, the status register is dynamic; the user is not requir ed to toggle re# / ce# to update it. the command register remains in status read mode until further commands are i ssued. therefor e, if the status register is read during a random read cycle, the read command (00h) must be issued before starting read cycles. note: the read status register command shall not be used for concurrent operations in multi-die stack configurations (single ce#). ?read status enhanced? shall be used instead. 3.10 read status enhanced ? s34ml02g1 and s34ml04g1 read status enhanced is used to retrieve the status value for a previous operation in the specified plane. figure 6.23 on page 55 defines the read status enhanced behavio r and timings. the plane and die address must be specified in the command sequence in order to re trieve the status of the di e and the plane of interest. refer to table 3.5 for specific status register definitions. the command register remains in status read mode until further commands are issued. the status register is dynamic; the user is not required to toggle re# / ce# to update it. table 3.4 page organization in edc units by address sector main field (column 0-2047) spare field (column 2048-2111) area name column address area name column address x8 1st 528-byte sector a 0-511 e 2048-2063 2nd 528-byte sector b 512-1023 f 2064-2079 3rd 528-byte sector c 1024-1535 g 2080-2095 4th 528-byte sector d 1536-2047 h 2096-2111 x16 1st 256-word sector a 0-255 e 1024-1031 2nd 256-word sector b 256-511 f 1032-1039 3rd 256-word sector c 512-767 g 1040-1047 4th 256-word sector d 768-1023 h 1048-1055 status register bit composite status value bit 0, pass/fail or bit 1, cache pass/fail or free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 29 data sheet 3.11 read status register field definition table 3.5 below lists the meaning of each bit of the r ead status register an d read status enhanced (s34ml02g1 and s34ml04g1). 3.12 reset the reset feature is executed by writing ffh to the command register. if the device is in the busy state during random read, program, or erase mode, the rese t operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data may be partially programmed or erased. the command register is cleared to wait for the next comman d, and the status register is cleared to value e0h when wp# is high or value 60h when wp# is low. if the device is already in reset state a new reset command will not be accepted by the command regi ster. the r/b# pin transitions to low for t rst after the reset command is written. refer to figure 6.24 on page 55 for further details. the status register can also be read to determine the st atus of a reset operation. 3.13 read cache read cache can be used to increase the read operation speed, as defined in section 3.1 on page 21 , and it cannot cross a block boundary. as soon as the user starts to read one page, the device automatically loads the next page into the cache register. serial data outpu t may be executed while data in the memory is read into the cache register. read cache is initiated by the page read sequence (00-30h) on a page m. after random access to the first page is complete (r /b# returned to high, or read status register i/o6 switches to high), two command sequences can be used to continue read cache: ? read cache (command ?31h? only): once the comm and is latched into the command register (see figure 6.26 on page 56 ), device goes busy for a short time (t cbsyr ), during which data of the first page is transferred from the data register to the cache register. at t he end of this phase, the cache register data can be output by toggling re# while the next page (pag e address m+1) is read from the memory array into the data register. ? read cache enhanced (sequence ?00h? ?31?): once the command is latched into the command register (see figure 6.27 on page 57 ), device goes busy for a short time (t cbsyr ), during which data of the first page is transferred from the data regi ster to the cache register. at the end of this phase, cache register data can be output by toggling re# while page n is read from the memory array into the data register. note : the S34ML01G1 device does not support read cache enhanced. table 3.5 status register coding id page program / page reprogram block erase read read cache cache program / cache reprogram coding 0 pass / fail pass / fail na na pass / fail n page pass: 0 fail: 1 1 na na na na pass / fail n - 1 page pass: 0 fail: 1 2na na na na na ? 3na na na na na ? 4na na na na na ? 5 ready / busy ready / busy ready / busy ready / busy ready / busy internal data operation active: 0 idle: 1 6 ready / busy ready / busy ready / busy ready / busy ready / busy ready / busy busy: 0 ready: 1 7 write protect write protect na na write protect protected: 0 not protected: 1 free datasheet http://www.datasheet-pdf.com/
30 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet subsequent pages are read by issuing additional read cache or read cache enhanced command sequences. if serial data output time of one page exceeds random access time (t r ), the random access time of the next page is hidden by data downloading of the previous page. on the other hand, if 31h is issued prior to completi ng the random access to the next page, the device will stay busy as long as needed to complete random access to this page, transfer its contents into the cache register, and trigger the random access to the following page. to terminate the read cache operation, 3fh command should be issued (see figure 6.28 on page 57 ). this command transfers data from the data register to the cache register without issuing next page read. during the read cache operation, the device doesn't allow any other command except for 00h, 31h, 3fh, read sr, or reset (ffh). to carry out other operati ons, read cache must be terminated by the read cache end command (3fh) or the device must be reset by issuing ffh. read status command (70h) may be issued to check t he status of the different registers and the busy/ready status of the cached read operations. ? the cache-busy status bit i/o6 indicates when the cache register is ready to output new data. ? the status bit i/o5 can be used to determine when the cell reading of the current data register contents is complete. note : the read cache and read cache end commands re set the column counter, thus, when re# is toggled to output the data of a given page, the first output data is related to the first byte of the page (column address 00h). random data output command can be used to switch column address. 3.14 cache program cache program can improve the program throughput by using the cache register. the cache program operation cannot cross a block boundary. the cache regist er allows new data to be input while the previous data that was transferred to the data register is programmed into the memory array. after the serial data input command (80h) is loaded to the command register, followed by five cycles of address, a full or partial page of data is latched into the cache register. once the cache write command (15h) is loaded to the command register, the data in the cache register is transferred into the data register for cell programming. at this time the device remains in the busy state for a short time (t cbsyw ). after all data of the cache r egister is transferred into the data register, the device returns to the ready state and allows loading the next data in to the cache register through another cache program command sequence (80h-15h). the busy time following the first sequence 80h - 15h equals the time needed to transfer the data from the cache register to the data register. cell programming the data of the data register and loading of the next data into the cache register is consequently processed through a pipeline model. in case of any subsequent sequence 80h - 15h, transfer from the cache register to the data register is held off until cell programming of current data register contents is complete; till this moment the device will stay in a busy state (t cbsyw ). read status commands (70h or 78h) may be issued to check the status of the di fferent regist ers, and the pass/fail status of the cached program operations. ? the cache-busy status bit i/o6 indicates when the cache register is ready to accept new data. ? the status bit i/o5 can be used to determine when the cell programming of the current data register contents is complete. ? the cache program error bit i/o1 can be used to identify if the previous page (page n-1) has been successfully programmed or not in a cache program opera tion. the status bit is valid upon i/o6 status bit changing to 1. ? the error bit i/o0 is used to identify if any error has been detected by the program/erase controller while programming page n. the status bit is valid upon i/o5 status bit changing to 1. i/o1 may be read together with i/o0. free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 31 data sheet if the system monitors the progress of the operation only with r/b#, t he last page of the target program sequence must be programmed with page progra m confirm command (10h). if the cache program command (15h) is used instead, the status bit i/o5 mu st be polled to find out if the last programming is finished before starting any other operation. see table 3.5 on page 29 and figure 6.29 on page 58 for more details. if a cache program operation is interrupted by hardwar e reset, power failure or other means, the host must ensure that the interrupted pages are not used for fu rther reading or programming operations until the next uninterrupted block eras es are complete for the applicable blocks. 3.15 multiplane cache program ? s34ml02g1 and s34ml04g1 the multiplane cache program enables high program throughput by programming two pages in parallel, while exploiting the data and cache regist ers of both planes to implement cache. the command sequence can be summarized as follows: ? serial data input command (80h), followed by the fi ve cycle address inputs and then serial data for the 1st page. address for this page must be within 1st plane (pla0 = 0). the data of 1s t page other than those to be programmed do not need to be loaded. the device supports random data input exactly like page program operation. ? the dummy page program confirm command (11h) stops 1st page data input and the device becomes busy for a short time (t dbsy ). ? once device returns to ready again, 81h command must be issued, followed by 2nd page address (5 cycles) and its serial data input. address for this page must be within 2nd plane (pla0 = 1). the data of 2nd page other than those to be programmed do not need to be loaded. ? cache program confirm command (15h). once the cac he write command (15h) is loaded to the command register, the data in the cach e registers is transferred into the data registers for cell programming. at this time the device remains in the busy state for a short time (t cbsyw ). after all data from the cache registers are transferred into the data registers, the device re turns to the ready state, and allows loading the next data into the cache register through another cache program command sequence. the sequence 80h-...- 11h...-...81h...-...15h can be iterat ed, and each time the device will be busy for the t cbsyw time needed to complete programming the current data register contents, and transferring the new data from the cache registers. the sequence to end multiplane cache program is 80h-...- 11h...-...81h...- ...10h. the multiplane cache program is available only within two paired blocks in separate planes. figure 6.30 on page 59 shows the legacy protocol for the multiplane ca che program operation. in this case, the block address bits for the first plane are all zero and the second address issued selects the block for both planes. figure 6.31 on page 60 shows the onfi protocol for the mult iplane cache program operation. for both addresses issued in this protocol, the block address bits mu st be the same except for the bit(s) that select the plane. the user can check operation status by r/b# pin or read status register commands (70h or 78h). if the user opts for 70h, read status register will provide ?global ? information about the operation in the two planes. ? i/o6 indicates when both cache registers are ready to accept new data. ? i/o5 indicates when the cell programming of the current data registers is complete. ? i/o1 identifies if the previous pages in both planes (pages n-1) have been successfully programmed or not. this status bit is valid upon i/o6 status bit changing to 1. ? i/o0 identifies if any error has been detected by the program/erase controller while programming the two pages n. this status bit is valid upon i/o5 status bit changing to 1. see table 3.5 on page 29 for more details. if the system monitors the progress of the operation only wit h r/b#, the last pages of the target program sequence must be programmed with page progra m confirm command (10h). if the cache program command (15h) is used instead, the status bit i/o5 mu st be polled to find out if the last programming is finished before starting any other operation. refer to section 3.9 on page 28 for further information. free datasheet http://www.datasheet-pdf.com/
32 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet if a multiplane cache program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupt ed pages are not used for further reading or programming operations until the next uninterrupted block erases are complete for the applicable blocks. 3.16 read id the device contains a product identification mode, initia ted by writing 90h to the command register, followed by an address input of 00h. note : if you want to execute read status command (0x70) after read id sequence, you should input dummy command (0x00) before read status command (0x70). for the s34ml02g1 and s34ml04g1 devices, five read cycles sequentially output the manufacturer code (01h), and the device code and 3rd, 4th, and 5th cycle id, respectively . for the S34ML01G1 device, four read cycles sequentially output the manufacturer code (01h), device id (f1h), 3rd cycle (00h), and 4th cycle id of 1dh respectively. the command register remains in re ad id mode until further commands are issued to it. figure 6.32 on page 61 shows the operation sequence, while table 3.6 to table 3.11 explain the byte meaning. table 3.6 read id for supported configurations density org v cc 1st 2nd 3rd 4th 5th 1 gb x8 3.3v 01h f1h 00h 1dh ? 2 gb 01h dah 90h 95h 44h 4 gb 01h dch 90h 95h 54h 1 gb x16 01h c1h 00h 5dh ? 2 gb 01h cah 90h d5h 44h 4 gb 01h cch 90h d5h 54h table 3.7 read id bytes device identifier byte description 1st manufacturer code 2nd device identifier 3rd internal chip number, cell type, etc. 4th page size, block size, spare size, serial access time, organization 5th (s34ml02g1, s34ml04g1) ecc, multiplane information free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 33 data sheet 3 rd id data 4 th id data table 3.8 read id byte 3 description description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 internal chip number 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2-level cell 4-level cell 8-level cell 16-level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 11 interleave program between multiple chips not supported supported 0 1 cache program not supported supported 0 1 table 3.9 read id byte 4 description ? S34ML01G1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (without spare area) 1 kb 2 kb 4 kb 8 kb 0 0 0 1 1 0 1 1 block size (without spare area) 64 kb 128 kb 256 kb 512 kb 0 0 0 1 1 0 1 1 spare area size (byte / 512 byte) 8 16 0 1 serial access time 45 ns 25 ns reserved reserved 0 0 1 1 0 1 0 1 organization x8 0 x16 1 free datasheet http://www.datasheet-pdf.com/
34 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 5 th id data 3.17 read id2 the device contains an alternate identification mode, initiated by writing 30h-65h-00h to the command register, followed by address inputs, followed by command 30h. the address for S34ML01G1 will be 00h-02h-02h-00h. the address for s34ml02g1 and s34ml04g1 will be 00 h-02h-02h-00h-00h. the id2 data can then be read from the device by pulsing re#. t he command register remains in read id2 mode until further commands are issued to it. figure 6.33 on page 61 shows the read id2 command sequence. read id2 values are all 0xfs, unless specific values are requested when ordering from spansion. 3.18 read onfi signature to retrieve the onfi signature, the command 90h together with an address of 20h shall be entered (i.e. it is not valid to enter an address of 00h and read 36 bytes to get the onfi signature). the onfi signature is the ascii encoding of 'onfi' wh ere 'o' = 4fh, 'n' = 4eh, 'f ' = 46h, and 'i' = 49h. reading beyond four bytes yields indeterminate values. figure 6.34 on page 62 shows the operation sequence. table 3.10 read id byte 4 description ? s34ml02g1 and s34ml04g1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (without spare area) 1 kb 2 kb 4 kb 8 kb 0 0 0 1 1 0 1 1 block size (without spare area) 64 kb 128 kb 256 kb 512 kb 0 0 0 1 1 0 1 1 spare area size (byte / 512 byte) 8 16 0 1 serial access time 50 ns / 30 ns 25 ns reserved reserved 0 1 0 1 0 0 1 1 organization x8 0 x16 1 table 3.11 read id byte 5 description ? s34ml02g1 and s34ml04g1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 plane number 1 2 4 8 0 0 0 1 1 0 1 1 plane size (without spare area) 64 mb 128 mb 256 mb 512 mb 1 gb 2 gb 4 gb 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 reserved 0 0 0 free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 35 data sheet 3.19 read parameter page the device supports the onfi read parameter page operation, initiated by writing ech to the command register, followed by an address input of 00h. the host may monitor the r/b# pin or wait for the maximum data transfer time (t r ) before reading the parameter page data. t he command register remains in parameter page mode until further commands are issued to it. if the status register is read to determine when the data is ready, the read command (00h) must be issued before starting read cycles. figure 6.35 on page 62 shows the operation sequence, while table 3.12 explains the parameter fields. for x16 devices, the upper eight i/os are not used and are 0xff. table 3.12 parameter page description (sheet 1 of 3) byte o/m description values revision information and features block 0-3 m parameter page signature byte 0: 4fh, ?o? byte 1: 4eh, ?n? byte 2: 46h, ?f? byte 3: 49h, ?i? 4fh, 4eh, 46h, 49h 4-5 m revision number 2-15 reserved (0) 1 1 = supports onfi version 1.0 0 reserved (0) 02h, 00h 6-7 m features supported 5-15 reserved (0) 4 1 = supports odd to even page copyback 3 1 = supports interleaved operations 2 1 = supports non-sequential page programming 1 1 = supports multiple lun operations 0 1 = supports 16-bit data bus width S34ML01G100 (x8) : 14h, 00h s34ml02g100 (x8) : 1ch, 00h s34ml04g100 (x8) : 1ch, 00h S34ML01G104 (x16) : 15h, 00h s34ml02g104 (x16) : 1dh, 00h s34ml04g104 (x16) : 1dh, 00h 8-9 m optional commands supported 6-15 reserved (0) 5 1 = supports read unique id 4 1 = supports copyback 3 1 = supports read status enhanced 2 1 = supports get features and set features 1 1 = supports read cache commands 0 1 = supports page cache program command S34ML01G1: 13h, 00h s34ml02g1: 1bh, 00h s34ml04g1: 1bh, 00h 10-31 reserved (0) 00h manufacturer information block 32-43 m device manufacturer (12 ascii characters) 53h, 50h, 41h, 4eh, 53h, 49h, 4fh, 4eh, 20h, 20h, 20h, 20h 44-63 m device model (20 ascii characters) S34ML01G1: 53h, 33h, 34h, 4dh, 4ch, 30h, 31h, 47h, 31h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h s34ml02g1: 53h, 33h, 34h, 4dh, 4ch, 30h, 32h, 47h, 31h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h s34ml04g1: 53h, 33h, 34h, 4dh, 4ch, 30h, 34h, 47h, 31h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h 64 m jedec manufacturer id 01h 65-66 o date code 00h 67-79 reserved (0) 00h memory organization block 80-83 m number of data bytes per page 00h, 08h, 00h, 00h 84-85 m number of spare bytes per page 40h, 00h 86-89 m number of data bytes per partial page 00h, 02h, 00h, 00h 90-91 m number of spare bytes per partial page 10h, 00h free datasheet http://www.datasheet-pdf.com/
36 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 92-95 m number of pages per block 40h, 00h, 00h, 00h 96-99 m number of blocks per logical unit (lun) S34ML01G1: 00h, 04h, 00h, 00h s34ml02g1: 00h, 08h, 00h, 00h s34ml04g1: 00h, 10h, 00h, 00h 100 m number of logical units (luns) 01h 101 m number of address cycles 4-7 column address cycles 0-3 row address cycles S34ML01G1: 22h s34ml02g1: 23h s34ml04g1: 23h 102 m number of bits per cell 01h 103-104 m bad blocks maximum per lun S34ML01G1: 14h, 00h s34ml02g1: 28h, 00h s34ml04g1: 50h, 00h 105-106 m block endurance 01h, 05h 107 m guaranteed valid blocks at beginning of target 01h 108-109 m block endurance for guaranteed valid blocks 01h, 03h 110 m number of programs per page 04h 111 m partial programming attributes 5-7 reserved 4 1 = partial page layout is partial page data followed by partial page spare 1-3 reserved 0 1 = partial page programming has constraints 00h 112 m number of bits ecc correctability 01h 113 m number of interleaved address bits 4-7 reserved (0) 0-3 number of interleaved address bits S34ML01G1: 00h s34ml02g1: 01h s34ml04g1: 01h 114 o interleaved operation attributes 4-7 reserved (0) 3 address restrictions for program cache 2 1 = program cache supported 1 1 = no block address restrictions 0 overlapped / concurrent interleaving support S34ML01G1: 00h s34ml02g1: 04h s34ml04g1: 04h 115-127 reserved (0) 00h electrical parameters block 128 m i/o pin capacitance 0ah 129-130 m timing mode support 6-15 reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0, shall be 1 1fh, 00h 131-132 o program cache timing mode support 6-15 reserved (0) 5 1 = supports timing mode 5 4 1 = supports timing mode 4 3 1 = supports timing mode 3 2 1 = supports timing mode 2 1 1 = supports timing mode 1 0 1 = supports timing mode 0 1fh, 00h 133-134 m t prog maximum page program time (s) bch, 02h 135-136 m t bers maximum block erase time (s) S34ML01G1: b8h, 0bh s34ml02g1: 10h, 27h s34ml04g1: 10h, 27h 137-138 m t r maximum page read time (s) 19h, 00h 139-140 m t ccs minimum change column setup time (ns) 64h, 00h 141-163 reserved (0) 00h vendor block table 3.12 parameter page description (sheet 2 of 3) byte o/m description values free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 37 data sheet note: 1. o? stands for optional, ?m? for mandatory. 3.20 one-time programmable (otp) entry the device contains a one-time programmable (otp) ar ea, which is accessed by writing 29h-17h-04h-19h to the command register. the device is then ready to accept page read and page program commands (refer to page read and page program on page 21 ). the otp area is of a single erase block size (64 pages), and hence only row addresses between 00h and 3fh are allowed. the host must issue the reset command (refer to reset on page 29 ) to exit the otp area and access the normal flash array. the block erase command is not allowed in the otp area. refer to figure 6.36 on page 63 for more detail on the otp entry command sequence. note: the otp feature in the S34ML01G1 do es not have non-volatile protection. 4. signal descriptions 4.1 data protection and power on / off sequence the device is designed to offer protection from any in voluntary program/erase during power-transitions. an internal voltage detector disables all functions whenever v cc is below about 1.8v. the power-up and power-down sequence is shown in figure 6.37 on page 63 , in this case v cc and v ccq on the one hand (and v ss and v ssq on the other hand) are shor ted together at all times. the ready/busy signal shall be valid within 100 s after the power supplies have reached the minimum values (as specified on), and shall return to one within 5 ms (max). during this busy time, the device executes the initialization process (cam reading), and dissipates a current i cc0 (30 ma max), in addition, it disregards all commands excluding read status register (70h). at the end of this busy time, the device defaults into ?read setup?, thus if the user decides to issue a page read command, the 00h command may be skipped. the wp# pin provides hardware protection and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 100 s is required before the internal circuit gets ready for any command sequences as shown in figure 6.37 on page 63 . the two-step command sequence for program/erase provides additional software protection. 164-165 m vendor specific revision number 00h 166-253 vendor specific 00h 254-255 m integrity crc S34ML01G100 (x8) : ffh, 63h s34ml02g100 (x8) : 3bh, c5h s34ml04g100 (x8) : 45h, 8eh S34ML01G104 (x16) : 8dh, 15h s34ml02g104 (x16) : 49h, b3h s34ml04g104 (x16) : 37h, f8h redundant parameter pages 256-511 m value of bytes 0-255 repeat value of bytes 0-255 512-767 m value of bytes 0-255 repeat value of bytes 0-255 768+ o additional redundant parameter pages ffh table 3.12 parameter page description (sheet 3 of 3) byte o/m description values free datasheet http://www.datasheet-pdf.com/
38 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 4.2 ready/busy the ready/busy output provides a method of indicating the completion of a page program, erase, copyback, or read completion. the r/b# pin is normally high and goes to low when the device is busy (after a reset, read, program, or erase operat ion). it returns to high when the internal controller has finished the operation. the pin is an open-drain driver thereby allowing two or more r/b# outputs to be or-tied. because the pull-up resistor value is related to t r (r/b#) and the current drain during busy (ibusy), and output load capacitance is related to t f an appropriate value can be obtained with the reference chart shown in figure 4.1 . for example, for a par ticular system with 20 pf of output load, t f from v cc to v ol at 10% to 90% will be 10 ns, whereas for a particular load of 50 pf, spansion measured it to be 20 ns as shown in figure 4.1 . figure 4.1 ready/busy pin electrical application rp v s . t r , t f a nd rp v s . i bus y rp i bus y b us y re a dy v cc v oh v ol v ol : 0.4v, v oh : 2.4v vcc gnd device open dr a in o u tp u t r/b# c l 3 00n 200n 100n = t f (n s ) 20 20 20 20 50 = t r (n s ) 3 m 2m 1m i bus y [a] t r ,t f [ s ] 1k 2k 3 k4k = i bus y ( ma ) 1.2 2.4 100 150 200 0. 8 0.6 rp (ohm) @ vcc = 3 . 3 v, t a = 25c, c l =50 pf rp v a l u e g u idence rp (min.) = = vcc (m a x.) - v ol (m a x.) 3 .2v 8ma + i l i ol + i l rp(m a x) i s determined b y m a xim u m permi ss i b le limit of tr. where i s the su m of the inp u t c u rrent s of a ll device s tied to the r/b# pin. l i t f t r legend free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 39 data sheet 4.3 write protect operation erase and program operations are aborted if wp# is driven low during busy time, and kept low for about 100 ns. switching wp# low during this time is equivalent to issuing a reset command (ffh). the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the r/b# pin will stay low for t rst (similarly to figure 6.24 on page 55 ). at the end of this time, the command register is ready to process the next command, and the status register bit i/ o6 will be cleared to 1, while i/o7 value will be related to the wp# value. refer to table 3.5 on page 29 for more information on device status. erase and program operations are enabled or disabled by setting wp# to high or low respectively, prior to issuing the setup commands (80h or 60h). the level of wp# shall be set t ww ns prior to raising the we# pin for the set up command, as explained in figure 6.38 and figure 6.39 on page 64 . figure 4.2 wp# low timing requirements during program/erase command sequence we# i/o[7:0] wp# v a lid > 100 n s s e qu ence a b orted free datasheet http://www.datasheet-pdf.com/
40 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 5. electrical characteristics 5.1 valid blocks 5.2 absolute maximum ratings notes: 1. except for the rating ?operating temperature r ange?, stresses above those listed in the table absolute maximum ratings ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and operation of the device at these o r any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute max imum rating conditions for extended periods may affect device reliability. 2. minimum voltage may undershoot to -2v during tr ansition and for less than 20 ns during transitions. 3. maximum voltage may overshoot to vcc+2.0v during transition and for less than 20 ns during transitions. 5.3 ac test conditions table 5.1 valid blocks device symbol min typ max unit S34ML01G1 n vb 1004 ? 1024 blocks s34ml02g1 n vb 2008 ? 2048 blocks s34ml04g1 n vb 4016 ? 4096 blocks table 5.2 absolute maximum ratings parameter symbol value unit ambient operating temperature (industrial temperature range) t a -40 to +85 c temperature under bias t bias -50 to +125 c storage temperature t stg -65 to +150 c input or output voltage v io (2) -0.6 to +4.6 v supply voltage v cc -0.6 to +4.6 v table 5.3 ac test conditions parameter value input pulse levels 0.0v to v cc input rise and fall times 5 ns input and output timing levels v cc / 2 output load (2.7v - 3.6v) 1 ttl gate and cl = 50 pf free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 41 data sheet 5.4 ac characteristics notes: 1. the time to ready depends on the value of the pull-up resistor tied to r/b# pin. 2. if reset command (ffh) is written at ready state, the device goes into busy for maximum 5 s. 3. ce# low to high or re# low to high can be at different times and produce three cases. depending on which signal comes high fi rst, either t coh or t rhoh will be met. 4. during data output, t cea depends partly on t cr (ce# low to re# low). if t cr exceeds the minimum value specified, then the maximum time for t cea may also be exceeded (t cea = t cr + t rea ). table 5.4 ac characteristics parameter symbol min max unit ale to re# delay t ar 10 ? ns ale hold time t alh 5?ns ale setup time t als 10 ? ns address to data loading time t adl 70 ? ns ce# low to re# low t cr 10 ? ns ce# hold time t ch 5?ns ce# high to output high-z t chz ?30ns cle hold time t clh 5?ns cle to re# delay t clr 10 ? ns cle setup time t cls 10 ? ns ce# access time t cea (4) ?25ns ce# high to output hold t coh (3) 15 ? ns ce# high to ale or cle don't care t csd 10 ? ns ce# setup time t cs 20 ? ns data hold time t dh 5?ns data setup time t ds 10 ? ns data transfer from cell to register t r ?25s output high-z to re# low t ir 0?ns read cycle time t rc 25 ? ns re# access time t rea ?20ns re# high hold time t reh 10 ? ns re# high to output hold t rhoh (3) 15 ? ns re# high to we# low t rhw 100 ? ns re# high to output high-z t rhz ? 100 ns re# low to output hold t rloh 5?ns re# pulse width t rp 12 ? ns ready to re# low t rr 20 ? ns device resetting time (read/program/erase) t rst ? 5/10/500 s we# high to busy t wb ? 100 ns write cycle time t wc 25 ? ns we# high hold time t wh 10 ? ns we# high to re# low t whr 60 ? ns we# pulse width t wp 12 ? ns write protect time t ww 100 ? ns free datasheet http://www.datasheet-pdf.com/
42 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 5.5 dc characteristics notes: 1. all v ccq and v cc pins, and v ss and v ssq pins respectively are shorted together. 2. values listed in this table refer to the complete voltage range for v cc and v ccq and to a single device in case of device stacking. 3. all current measurements are performed with a 0.1 f capacitor connected between the v cc supply voltage pin and the v ss ground pin. 4. standby current measurement can be performed after the device has completed the initialization process at power up. refer to section 4.1 for more details. 5.6 pin capacitance note: 1. for the stacked devices version the input is 10 pf x [number of stacked chips] and the input/output is 10 pf x [number of sta cked chips]. table 5.5 dc characteristics and operating conditions parameter symbol test conditions min typ max units power-on current (s34ml02g1, s34ml04g1) i cc0 power-up current (refer to section 4.1 ) ?1530ma operating current sequential read i cc1 t rc = see table 5.4 ce#=v il , i out = 0 ma ?1530ma program i cc2 normal ( S34ML01G1) ?1530ma normal (s34ml02g1) ?1530ma normal (s34ml04g1) ??30ma cache (s34ml02g1) ?2040ma cache (s34ml04g1) ??40ma erase i cc3 ? (S34ML01G1) ?1530ma ? (s34ml02g1) ??30ma ? (s34ml04g1) ?1530ma standby current, (ttl) i cc4 ce# = v ih , wp# = 0v/vcc ?? 1ma standby current, (cmos) i cc5 ce# = v cc ?0.2, wp# = 0/v cc ?1050a input leakage current i li v in = 0 to 3.6v ? ? 10 a output leakage current i lo v out = 0 to 3.6v ? ? 10 a input high voltage v ih ?v cc x 0.8 ? v cc + 0.3 v input low voltage v il ?-0.3?v cc x 0.2 v output high voltage v oh i oh = ?400 a 2.4 ? ? v output low voltage v ol i ol = 2.1 ma ? ? 0.4 v output low current (r/b#) i ol(r/b#) v ol = 0.4v 8 10 ? ma v cc supply voltage (erase and program lockout) v lko ??1.8?v table 5.6 pin capacitance (ta = 25c, f=1.0 mhz) parameter symbol test condition min max unit input c in v in = 0v ? 10 pf input / output c io v il = 0v ? 10 pf free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 43 data sheet 5.7 program / erase characteristics notes: 1. typical program time is defined as the time within which more than 50% of the whole pages are programmed (v cc = 3.3v, 25c). 2. copy back read and copy back program for a given plane must be between odd address pages or between even address pages for th e device to meet the program time (t prog ) specification. copy back program may not meet this specification when copying from an odd address page (source page) to an even address page (target page) or from an even address page (source page) to an odd address p age (target page). 6. timing diagrams 6.1 command latch cycle command input bus operation is used to give a co mmand to the memory device. commands are accepted with chip enable low, command latch enable high, address latch enable low, and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modify operation (write/ erase) the write prot ect pin must be high. figure 6.1 command latch cycle table 5.7 program / erase characteristics parameter description min typ max unit program time / multiplane program time (2) t prog ? 200 700 s dummy busy time for multiplane program ( s34ml02g1, s34ml04g1) t dbsy ?0.5 1 s cache program short busy time ( s34ml02g1, s34ml04g1) t cbsyw ?5t prog s number of partial program cycles in the same page main + spare nop ? ? 4 cycle block erase time / multiplane erase time ( s34ml02g1, s34ml04g1) t bers ?3.510ms block erase time ( S34ML01G1) t bers ?2 3ms read cache busy time t cbsyr ?3t r s tcl s tc s twp comm a nd cle ce# we# ale i/ox tdh td s tal s talh tclh tch = don ? t c a re free datasheet http://www.datasheet-pdf.com/
44 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 6.2 address latch cycle address input bus operation allows the insertion of the memory address. to insert the 27 (x8 device) addresses needed to access the 1 gb, four write cyc les are needed. addresses are accepted with chip enable low, address latch enable high, command latch enable low, and read enable high and latched on the rising edge of write enable. moreover, for commands th at start a modify operation (write/ erase) the write protect pin must be high. figure 6.2 address latch cycle 6.3 data input cycle timing data input bus operation allows the data to be programme d to be sent to the device. the data insertion is serially, and timed by the write enable cycles. data is accepted only with chip en able low, address latch enable low, command latch enable low, read enable hi gh, and write protect high a nd latched on the rising edge of write enable. figure 6.3 input data latch cycle tcl s tc s twc tal s tal s tal s tal s tal s talh talh talh talh twc twc twc twp twp twh twp twp twh twh twh td s col. add1 cle ce# we# ale i/ox td s td s td s td s tdh tdh tdh tdh tdh col. add2 row. add2 row. add1 row. add 3 talh = don ? t c a re twc tclh tch twp twh din twh tdh tdh tdh td s td s td s twp twp cle ale ce# i/ox we# tal s din 0 din fin a l = don ? t c a re free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 45 data sheet 6.4 data output cycle timing (c le=l, we#=h, ale=l, wp#=h) figure 6.4 data output cycle timing notes: 1. transition is measured at 200 mv from steady state voltage with load. 2. this parameter is sampled and not 100% tested. 3. t rhoh starts to be valid when frequency is lower than 33 mhz. 6.5 data output cycle timing (edo type, cle=l, we#=h, ale=l) figure 6.5 data output cycle timing (edo) notes: 1. transition is measured at 200 mv from steady state voltage with load. 2. this parameter is sampled and not 100% tested. 3. t rloh is valid when frequency is higher than 33 mhz. 4. t rhoh starts to be valid when frequency is lower than 33 mhz. trc ce# re# i/ox r/b# trea trr t u o d t u o d t u o d trea trhz trea tchz tcoh trhoh treh trhz trc trp treh trea tcr trloh trr trea tchz tcoh trhz trhoh do u t do u t ce# re# i/ox r/b# = don ? t c a re free datasheet http://www.datasheet-pdf.com/
46 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 6.6 page read operation figure 6.6 page read operation (read one page) note: 1. if status register polling is used to determine completion of the read operation, the read command (00h) must be issued befor e data can be read from the page buffer. 6.7 page read operation (interrupted by ce#) figure 6.7 page read operation interrupted by ce# ce# we# i/ox cle re# r/b# ale 00h col. add. 1 col. add. 2 row add. 1 row add. 2 row add. 3 3 0h do u t n do u t n +1 col u mn addre ss row addre ss tc s d twb tclr tr trc trr b us y tar do u t m trhz twc = don ? t c a re ce# we# i/ox cle re# r/b# ale 00h col. add. 1 col. add. 2 row add. 1 row add. 2 row add. 3 3 0h do u t n do u t n +1 col u mn addre ss row addre ss tc s d twb tclr tr trc trr b us y tar tchz tcoh do u t n +2 = don ? t c a re free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 47 data sheet 6.8 page read operation timing with ce# don?t care figure 6.8 page read operation timing with ce# don?t care 6.9 page program operation figure 6.9 page program operation note: 1. t adl is the time from the we# rising edge of final address cycle to the we# rising edge of first data cycle. 00h col. add. 1 col. add. 2 row add. 1 row add. 2 do u t n do u t n + 1 : don ? t c a re (v ih or v il ) ce# re# trea tcr ce# don ? t c a re ce# cle ale we# re# i/ox 3 0h do u t n + 2 do u t n + 3 do u t n + 4 do u t n + 5 do u t m do u t m + 1 do u t m + 2 r/b# tr trr trc i/ox do u t row add. 3 cle ale ce# re# r/b# i/ox we# twc s eri a l d a t a inp u t comm a nd col u mn addre ss row addre ss re a d s t a t us comm a nd progr a m comm a nd i/o0=0 su cce ss f u l progr a m i/o0=1 error in progr a m 1 u p to m b yte s eri a l inp u t din n din m twc twb tprog twhr twc tadl 8 0h col. add1 col. add2 row. add1 row. add2 h 0 7 h 0 1 i/o0 row. add 3 = don ? t c a re free datasheet http://www.datasheet-pdf.com/
48 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 6.10 page program operation timing with ce# don?t care figure 6.10 page program operation ti ming with ce# don?t care 6.11 page program operatio n with random data input figure 6.11 random data input notes: 1. t adl is the time from the we# rising edge of final address cycle to the we# rising edge of first data cycle. 2. for edc operation only one random data input is allowed at each edc unit. 8 0h col. add. 1 col. add. 2 row add. 1 row add. 2 din n din n + 1 din m din p din p + 1 din r 10h : don ? t c a re ce# we# twp tc s tch ce# don ? t c a re ce# cle ale we# re# i/ox row add. 3 cle ale ce# re# r/b# i/ox we# 8 0h din n din m din j din k 8 5h 10h 70h s eri a l d a t a inp u t comm a nd r a ndom d a t a inp u t comm a nd col u mn addre ss col u mn addre ss s eri a l inp u t progr a m comm a nd re a d s t a t us comm a nd tprog io0 twb col. add1 col. add2 row add1 row add2 row add 3 col. add1 col. add2 tadl row addre ss twc twc tadl twc twhr = don ? t c a re free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 49 data sheet 6.12 random data output in a page figure 6.12 random data output 6.13 multiplane page program operation ? s34ml02g1 and s34ml04g1 figure 6.13 multiplane page program notes: 1. any command between 11h and 81h is prohibited except 70h, 78h, and ffh. 2. a18 is the plane address bit for x8 devices. a17 is the plane address bit for x16 devices. ce# we# i/ox cle re# r/b# ale 00h col. add. 1 col. add. 2 row add. 1 row add. 2 row add. 3 3 0h do u t n do u t n +1 05h col. add. 1 col. add. 2 do u t m do u t m +1 e0h col u mn addre ss row addre ss col u mn addre ss tclr twhr trea twb tar trhw tr trc trr b us y = don ? t c a re cle ale ce# re# r/b# i/ox we# r/b# i/o0 ~ 7 ex.) addre ss re s triction for m u ltipl a ne p a ge progr a m 8 1h 70h io progr a m confirm comm a nd (tr u e) tdb s y col add 1,2 a nd row add 1,2, 3 (2112 b yte d a t a ) a0 ~ a11: v a lid a12 ~ a17: fixed ? low ? a1 8 : fixed ? low ? a19 ~ a2 8 : fixed ? low ? s eri a l d a t a inp u t comm a nd col u mn addre ss p a ge row addre ss 1 u p to 2112 b yte d a t a s eri a l inp u t progr a m comm a nd (d u mmy) 11h 10h din n din m din n din m col. add1 8 0h col. add2 row add1 row add2 row add 3 twb tprog twb tdb s y col. add1 col. add2 row add1 row add2 row add 3 twc re a d s t aus comm a nd twhr tprog 8 0h addre ss & d a t a inp u t 11h col add 1,2 a nd row add 1,2, 3 (2112 b yte d a t a ) a0 ~ a11: v a lid a12 ~ a17: v a lid a1 8 : fixed ? high ? a19 ~ a2 8 : v a lid tadl tadl 8 1h addre ss & d a t a inp u t 10h 70h (note 1) free datasheet http://www.datasheet-pdf.com/
50 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet figure 6.14 multiplane page program (onfi 1.0 protocol) notes: 1. c1a-c2a column address for page a. c1a is the least significant byte. 2. r1a-r3a row address for page a. r1a is the least significant byte. 3. d0a-dna data to program for page a. 4. c1b-c2b column address for page b. c1b is the least significant byte. 5. r1b-r3b row address for page b. r1b is the least significant byte. 6. d0b-dnb data to program for page b. 7. the block address bits must be the same except for the bit(s) that select the plane. 6.14 block erase operation figure 6.15 block erase operation (erase one block) cmd addr addr addr addr addr cmd addr addr addr addr addr din din din din din din din din cmd cmd 80h c1 a c2 a d0 a r3 a r2 a r1 a d1 a ... dn a 11h 80h c1 b c2 b d0 b r3 b r2 b r1 b d1 b ... dn b 10h cycle type dqx sr[6] cycle type dqx sr[6] a tadl tadl tadl tipbsy tadl tprog twc cle ce# we# ale re# i/ox r/b# twb tber s bu s y a u to block er as e s et u p comm a nd i/o0=0 su cce ss f u l er as e i/o0=1 error in er as e row addre ss d0h 60h 70h i/o0 er as e comm a nd re a d s t a t us comm a nd row add1 row add2 row add 3 twhr = don ? t c a re free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 51 data sheet 6.15 multiplane block erase ? s34ml02g1 and s34ml04g1 figure 6.16 multiplane block erase note: 1. a18 is the plane address bit for x8 devices. a17 is the plane address bit for x16 devices. figure 6.17 multiplane block erase (onfi 1.0 protocol) notes: 1. r1a-r3a row address for block on plane 0. r1a is the least significant byte. 2. r1b-r3b row address for block on plane 1. r1b is the least significant byte. 3. the block address bits must be the same except for the bit(s) that select the plane. row address block erase setup command1 block erase setup command2 erase confirm command read status command busy row address ex.) address restriction for multiplane block erase operation ale cle ce# re# r/b# i/ox we# r/b# i/o0~7 twc 60h 60h row add1,2,3 row add1,2,3 a12 ~ a17 : fixed low a18 : fixed low a19 ~ a28 : fixed low a12 ~ a17 : fixed low a18 : fixed high a19 ~ a28 : valid address address h 0 7 h 0 6 d0h h 0 d h 0 6 70h i/o0 row add1 row add1 row add2 row add2 3 d d a w o r 3 d d a w o r twc twb tbers tbers twhr i/o 1 = 0 successful erase i/o 1 = 1 error in plane 60h cle we# ale re# iox r1 a r2 a r3 a d1h 60h r1 b r2 b sr[6] t iebsy r3 b d0h t bers free datasheet http://www.datasheet-pdf.com/
52 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 6.16 copy back read with optional data readout figure 6.18 copy back read with optional data readout 6.17 copy back program operat ion with random data input figure 6.19 copy back program with random data input i/o r/b# b us y tr (re a d b us y time) b us y tprog (progr a m b us y time) 00h s o u rce add inp u t s 3 5h d a t a o u tp u t s 8 5h t a rget add inp u t s 10h 70h/ 7bh s r0/ edc reg re a d s t a t us regi s ter/ edc regi s ter i/o r/b# b us y tr (re a d b us y time) b us y tprog (progr a m b us y time) 00h s o u rce add inp u t s 3 5h 8 5h 2 cycle add inp u t s 10h unlimited n u m b er of repetition s 70h s r0 re a d s t a t us regi s ter 8 5h t a rget add inp u t s d a t a d a t a free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 53 data sheet 6.18 multiplane copy back progr am ? s34ml02g1 and s34ml04g1 figure 6.20 multiplane copy back program notes: 1. copy back program operation is allowed only within the same memory plane. 2. any command between 11h and 81h is prohibited except 70h, 78h, and ffh. 3. a18 is the plane address bit for x8 devices. a17 is the plane address bit for x16 devices. i/ox r/b# r/b# i/ox tr tr tdb s y tprog 1 1 00h add. (5 cycle s ) 3 5h col. add. 1, 2 a nd row add. 1, 2, 3 s o u rce addre ss on pl a ne 0 00h add. (5 cycle s ) 3 5h col. add. 1, 2 a nd row add. 1, 2, 3 s o u rce addre ss on pl a ne 1 8 5h add. (5 cycle s ) 11h col. add. 1, 2 a nd row add. 1, 2, 3 de s tin a tion addre ss a0 ~ a11 : fixed ? low ? a12 ~ a17 : fixed ? low ? a1 8 : fixed ? low ? a19 ~ a2 8 : fixed ? low ? 8 1h add. (5 cycle s ) col. add. 1, 2 a nd row add. 1, 2, 3 de s tin a tion addre ss a0 ~ a11 : fixed ? low ? a12 ~ a17 : v a lid a1 8 : fixed ? high ? a19 ~ a2 8 : v a lid 10h 70h pl a ne 0 (1) ( 3 ) d a t a field s p a re field pl a ne 1 (2) ( 3 ) d a t a field s p a re field s o u rce p a ge s o u rce p a ge t a rget p a ge t a rget p a ge (1) : copy b a ck re a d on pl a ne 0 (2) : copy b a ck re a d on pl a ne 1 ( 3 ) : m u ltipl a ne copy b a ck progr a m (note 2) free datasheet http://www.datasheet-pdf.com/
54 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet figure 6.21 multiplane copy back program (onfi 1.0 protocol) notes: 1. c1a-c2a column address for page a. c1a is the least significant byte. 2. r1a-r3a row address for page a. r1a is the least significant byte. 3. c1b-c2b column address for page b. c1b is the least significant byte. 4. r1b-r3b row address for page b. r1b is the least significant byte. 5. the block address bits must be the same except for the bit(s) that select the plane. 6.19 read status register timing figure 6.22 status / edc read cycle 85h cle we# ale re# iox c1 a c2 a r1 a r2 a r3 a 11h 85h c1 b c2 b sr[6] a t ipbsy r1 b r2 b r3 b 10h t prog tcl s t clr t clh t c s t ch t wp t whr t cea t d s t rea t chz t coh t rhz t rhoh 70h or 7bh s t a t us o u tp u t t dh t ir ce# we# i/ox cle re# = don ? t c a re free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 55 data sheet 6.20 read status enhanced timing figure 6.23 read status enhanced timing 6.21 reset operation timing figure 6.24 reset operation timing cle ale we# i/o0-7 re# 7 8 h r1 r2 s r r 3 twhr tar ff t r s t we# ale cle re# i/o7:0 r/b# free datasheet http://www.datasheet-pdf.com/
56 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 6.22 read cache figure 6.25 read cache operation timing figure 6.26 ?sequential? read cache timing, start (and continuation) of cache operation p a ge n p a ge n p a ge n + 1 p a ge n + 2 p a ge n + 1 p a ge n + 3 p a ge n + 2 p a ge n + 3 d a t a c a che p a ge b u ffer cell arr a y p a ge n p a ge n + 1 p a ge n + 2 p a ge n + 3 1 1 2 3 3 4 5 5 6 7 7 8 9 ce# cle ale we# re# i/ox r/b# ce# cle ale we# re# i/ox r/b# a a 1 2 3 7 8 9 6 00h col. add 1 col. add 2 col u mn addre ss 00h row add 1 row add 2 p a ge addre ss n 3 0h 3 1h do u t 0 do u t 1 do u t 3 1h do u t 0 do u t 1 col. add. 0 p a ge n + 2 3 fh do u t 0 do u t 1 do u t 3 1h do u t 0 do u t do u t 1 do u t twc twb tr tcb s yr twb trr twb col. add. 0 p a ge n col. add. 0 p a ge n + 1 trc trc trr tcb s yr tcb s yr twb trr trc tcb s yr twb trr trc col. add. 0 p a ge n + 3 = don ? t c a re row add 3 4 5 5 cmd cmd dout dout dout cmd dout 0 d h 0 3 31h ... dn 31h d0 cycle type i/ox sr[6] trr as defined for read trr twb tr twb tcbsyr twb tcbsyr free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 57 data sheet figure 6.27 ?random? read cache timing, start (and continuation) of cache operation figure 6.28 read cache timing, en d of cache operation cycle type i/ox s r[6] cycle type i/ox s r[6] a s defined for re a d a cmd addr addr addr addr twb tr a addr cmd 00h c1 c2 r1 r2 r 3 3 1h cmd 3 0h do u t do u t do u t d0 . . . dn pa g e n pa g e r cmd addr addr addr addr addr cmd 00h c1 c2 r1 r2 r 3 3 1h do u t d0 trr twb tcb s yr trr twb tcb s yr trr cycle type i/ox s r[6] a s defined for re a d c a che ( s e qu enti a l or r a ndom) do u t do u t do u t cmd twb tcb s yr d0 . . . dn 3 fh cmd 3 1h do u t do u t do u t d0 . . . dn trr twb tcb s yr trr free datasheet http://www.datasheet-pdf.com/
58 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 6.23 cache program figure 6.29 cache program col u mn addre ss row addre ss twb col u mn addre ss row addre ss tcb s yw 1 1 cle ale ce# re# r/b# i/ox we# tcb s yw din n din m din n din m col u mn addre ss row addre ss 10h din n din m 70h tprog 8 0h col. add1 col. add2 row. add1 row. add2 row. add 3 15h 8 0h 15h 8 0h col. add1 col. add2 row. add1 row. add2 row. add 3 tadl s t a t us twc col. add1 col. add2 row. add1 row. add2 row. add 3 twc twc cle ale ce# re# r/b# i/ox we# free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 59 data sheet 6.24 multiplane cache program ? s34ml02g1 and s34ml04g1 figure 6.30 multiplane cache program notes: 1. read status register (70h) is used in the fi gure. read status enhanced (78h) can be also used. 2. a18 is the plane address bit for x8 devices. a17 is the plane address bit for x16 devices. cle ale ce# re# r/b# i/ox we# col u mn addre ss row addre ss twb twc col u mn addre ss row addre ss tcb s yw 1 1 tdb s y 8 0h col. add1 col. add2 row add1 row add2 row add 3 8 1h col. add1 col. add2 row add1 row add2 row add 3 15h din n din m 11h din n din m col u mn addre ss row addre ss twc col u mn addre ss row addre ss tprog tdb s y 11h din n din m 8 0h 8 1h col. add1 col. add2 row add1 row add2 row add 3 10h din n din m twb tadl tadl twb s t a t us 70h 8 0h addre ss inp u t d a t a inp u t 11h 8 1h addre ss inp u t d a t a inp u t 15h comm a nd inp u t a1 3~ a17: fixed ? low ? a1 8 : fixed ? low ? a19 ~ a 3 1: fixed ? low ? a1 3~ a17: v a lid a1 8 : fixed ? high ? a19 ~ a 3 1: v a lid t db s y ret u rn to 1 repe a t a m a x of 6 3 time s 8 0h addre ss inp u t d a t a inp u t 11h 8 1h addre ss inp u t d a t a inp u t 10h comm a nd inp u t a1 3~ a17: fixed ? low ? a1 8 : fixed ? low ? a19 ~ a 3 1: fixed ? low ? a1 3~ a17: v a lid a1 8 : fixed ? high ? a19 ~ a 3 1: v a lid t db s y t prog t cb s yw ry/by# ry/by# 1 1 cle ale ce# re# r/b# i/ox we# col. add1 col. add2 row add1 row add2 row add 3 free datasheet http://www.datasheet-pdf.com/
60 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet figure 6.31 multiplane cache program (onfi 1.0 protocol) notes: 1. the block address bits must be the same except for the bit(s) that select the plane. 2. read status register (70h) is used in the fi gure. read status enhanced (78h) can be also used. cle ale ce# re# r/b# iox we# col u mn addre ss row addre ss twb twc col u mn addre ss row addre ss tcb s yw 1 1 cle ale ce# re# r/b# iox we# tdb s y 11h din n din m 8 0h col. add1 col. add2 row add1 row add2 row add 3 8 0h col. add1 col. add2 row add1 row add2 row add 3 15h din n din m col u mn addre ss row addre ss twc col u mn addre ss row addre ss tprog tdb s y 11h din n din m 8 0h col. add1 col. add2 row add1 row add2 row add 3 8 0h col. add1 col. add2 row add1 row add2 row add 3 10h din n din m twb tadl tadl twb s t a t us 70h 8 0h addre ss inp u t d a t a inp u t 11h 8 0h addre ss inp u t d a t a inp u t 15h comm a nd inp u t t db s y ret u rn to 1 repe a t a m a x of 6 3 time s 8 0h addre ss inp u t d a t a inp u t 11h 8 0h addre ss inp u t d a t a inp u t 10h comm a nd inp u t t db s y t prog t cb s yw ry/by# ry/by# 1 1 free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 61 data sheet 6.25 read id operation timing figure 6.32 read id operation timing 6.26 read id2 operation timing figure 6.33 read id2 operation timing notes: 1. 4-cycle address is shown for the S34ML01G1. for s34ml02g1 and s34ml04g1, insert an additional address cycle of 00h. 2. if status register polling is used to determine completion of the read id2 operation, the read command (00h) must be issued b efore id2 data can be read from the flash. ce# we# cle re# ale twhr tar trea i/ox 01h f1h 00h 1dh 1 g b device i/ox 01h dah 90h 95h 2 g b device 44h i/ox 01h dch 90h 95h 4 g b device 54h re a d id comm a nd addre ss 1 cycle m a ker code device code 3 rd cycle 4th cycle 5th cycle 90h 90h 09h 00h 00h 00h ce# we# cle re# ale tr re a d id2 comm a nd s 4 cycle addre ss 1 s t cycle 2nd cycle 3 rd cycle 4th cycle 5th cycle i/ox re a d id2 confirm comm a nd 3 0h 65h 00h 00h 02h 02h 00h 3 0h id2 d a t a id2 d a t a id2 d a t a id2 d a t a id2 d a t a r/b# b us y (note 1) free datasheet http://www.datasheet-pdf.com/
62 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 6.27 read onfi signature timing figure 6.34 onfi signature timing 6.28 read parameter page timing figure 6.35 read parameter page timing note: 1. if status register polling is used to determine completion of the read operation, the read command (00h) must be issued befor e data can be read from the page buffer. 90h cle we# ale re# io0 ~ 7 20h 4fh t 4eh 46h whr 49h trea 00h cle we# ale re# io0-7 p1 r/b# ... ... t r 1 p0 1 p1 0 p0 0 ech free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 63 data sheet 6.29 otp entry timing figure 6.36 otp entry timing 6.30 power on and data protection timing figure 6.37 power on and data protection timing note: 1. v th = 1.8 volts. cle ale we# i/o0-7 29h 17h 19h 04h vcc v vcc(min) 100 s max invalid 0v ce v il v operation 5 ms max ih v il wp ready/busy dont care dont care dont care vcc(min) v th th free datasheet http://www.datasheet-pdf.com/
64 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 6.31 wp# handling figure 6.38 program enabling / disabling through wp# handling figure 6.39 erase enabling / disabling through wp# handling t 8 0h 10h ww we# i/ox wp# r/b# t 8 0h 10h ww we# i/ox wp# r/b# t 60h d0h ww t 60h d0h ww we# i/ox wp# r/b# we# wp# r/b# i/ox free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 65 data sheet 7. physical interface 7.1 physical diagram 7.1.1 48-pin thin small outline package (tsop1) figure 7.1 ts/tsr 48 ? 48-lead plastic thin small outline, 12 x 20 mm, package outline 5006 \ f16-038 \ 6.5.13 package ts/tsr 48 jedec mo-142 (d) dd symbol min nom max a --- --- 1.20 a1 0.05 --- 0.15 a2 0.95 1.00 1.05 b1 0.17 0.20 0.23 b 0.17 0.22 0.27 c1 0.10 --- 0.16 c 0.10 --- 0.21 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 e 11.90 12.00 12.10 e 0.50 basic l 0.50 0.60 0.70 o 0? --- 8 r 0.08 --- 0.20 n48 notes: 1. dimensions are in millimeters (mm). (dimensioning and tolerancing conform to ansi y14.5m-1994). 2. pin 1 identifier for standard pin out (die up). 3. pin 1 identifier for reverse pin out (die down): ink or laser mark. 4. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 5. dimensions d1 and e do not include mold protrusion. allowable mold protrusion on e is 0.15mm per side and on d1 is 0.25mm per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of b dimension at max. material condition. dambar cannot be located on lower radius or the foot. minimum space between protrusion and an adjacent lead to be 0.07mm. 7. these dimensions apply to the flat section of the lead between 0.10mm and 0.25mm from the lead tip. 8. lead coplanarity shall be within 0.10mm as measured from the seating plane. 9. dimension "e" is measured at the centerline of the leads. free datasheet http://www.datasheet-pdf.com/
66 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 7.1.2 63-pin ball grid array (bga) figure 7.2 vbm063 ? 63-pin bga, 11 mm x 9 mm package g5011\ 16-038.25 \ 6.5.13 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 3, spp-020. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the total number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0. when there is an even number of solder balls in the outer row, sd = ed/2 and se = ee/2. 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbm 063 jedec m0-207(m) 11.00 mm x 9.00 mm nom package symbol min nom max note a --- --- 1.00 profile a1 0.25 --- --- ball height d 11.00 bsc. body size e 9.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 63 ball count b 0.40 0.45 0.50 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc. ball pitch sd 0.40 bsc. solder ball placement se 0.40 bsc. solder ball placement a3-a8,b2-b8,c1,c2,c9,c10 depopulated solder balls d1,d2,d9,d10,e1,e2,e9,e10 f1,f2,f9,f10,g1,g2,g9,g10 h1,h2,h9,h10,j1,j2,j9,j10 k1,k2,k9,k10 l3-l8,m3-m8 free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 67 data sheet 8. system interface to simplify system interface, ce# may be unasserted during data loading or sequ ential data reading as shown in figure 8.1 . by operating in this way, it is possible to connect nand flash to a microprocessor. figure 8.1 program operation with ce# don't care figure 8.2 read operation with ce# don't care ce# don ? t c a re h 0 1 t u p n i a t a d (5 cycle) . d d a t r a t s h 0 8 d a t a inp u t cle ce# we# ale i/ox ce# don ? t c a re h 0 3 h 0 0 cle ce# re# ale r/b# we# i/ox ) l a i t n e u q e s ( t u p t u o a t a d (5 cycle) . d d a t r a t s tr free datasheet http://www.datasheet-pdf.com/
68 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet figure 8.3 page programming within a block p a ge 6 3 p a ge 3 1 p a ge 2 p a ge 1 p a ge 0 p a ge 6 3 p a ge 3 1 p a ge 2 p a ge 1 p a ge 0 (64) ( 3 2) ( 3 ) (2) (1) (64) (1) ( 3 ) ( 3 2) (1) d a t a regi s ter d a t a regi s ter from the l s b p a ge to m s b p a ge data in : d a t a (1) d a t a (64) ex.) r a ndom p a ge progr a m (option a l) data i n : d a t a (1) d a t a (64) free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 69 data sheet 9. error management 9.1 system bad block replacement over the lifetime of the device, additional bad blocks may develop. in this case, each bad block has to be replaced by copying any valid data to a new block. these additional bad blocks can be identified whenever a program or erase operation reports ?fail? in the status register. the failure of a page program operation does not affect t he data in other pages in the same block, thus the block can be replaced by re-programming the current da ta and copying the rest of the replaced block to an available valid block. refer to table 9.1 and figure 9.1 for the recommended procedure to follow if an error occurs during an operation. figure 9.1 bad block replacement notes: 1. an error occurs on the nth page of block a during a program operation. 2. data in block a is copied to the same location in block b, which is a valid block. 3. the nth page of block a, which is in controller buffer memory, is copied into the nth page of block b. 4. bad block table should be updated to prevent from erasing or programming block a. table 9.1 block failure operation recommended procedure erase block replacement program block replacement read ecc (1 bit / 512+16 byte) d a t a bu ffer memory of the controller n p a ge ffh d a t a ffh f a il u re th n p a ge th block a block b (1) (2) (3) free datasheet http://www.datasheet-pdf.com/
70 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 9.2 bad block management devices with bad blocks have the same quality level and the same ac and dc characteristics as devices where all the blocks are valid. a b ad block does not affect the performa nce of valid blocks because it is isolated from the bit line and common source line by a se lect transistor. the devices are supplied with all the locations inside valid blocks erased (f fh). the bad block information is wr itten prior to sh ipping. any block where the 1st byte in the spare area of the 1st or 2nd or last page does not contain ffh is a bad block. that is, if the first page has an ff value and should have been a non-ff value, then the non-ff value in the second page or the last page will indicate a bad block.the bad block information must be read before any erase is attempted, as t he bad block information may be erased. for the system to be able to recognize the bad blocks based on the original in formation, it is recommended to cr eate a bad block table following the flowchart shown in figure 9.2 . the host is responsible to detect and track bad blocks, both factory bad blocks and blocks that may go bad duri ng operation. once a block is found to be bad, data should no t be written to that block.the 1st block, which is placed on 00h block address is guaranteed to be a valid block. figure 9.2 bad block management flowchart note: 1. check for ffh at the 1st byte in the spare area of the 1st, 2nd, and last pages. ye s ye s no no s t a rt block addre ss = block 0 d a t a =ffh? l as t block? end increment block addre ss upd a te b a d block t ab le (1) free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 71 data sheet 10. ordering information the ordering part number is formed by a valid combination of the following: valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. notes: 1. bga package marking omits the leading ?s34? and the packing type designator from the ordering part number. 2. a, v, b: 4g x16 (04 in bus width) available, but for other x16 versions contact factory. s34ml 04g 1 00 t f i 00 0 packing type 0 = tray 3 = 13? tape and reel model number 00 = standard interface / onfi (x8) 00 = standard interface (x16) 01 = onfi (x16) temperature range i = industrial (?40c to + 85c) a = ?40c to + 85c, gt-grade v = automotive (?40c to + 105c) b = ?40c to + 105c, gt-grade materials set f = lead (pb)-free h = lead (pb)-free and low halogen package b=bga t = tsop bus width 00 = x8 nand, single die 04 = x16 nand, single die technology 1 = spansion nand revision 1 (4x nm) density 01g = 1 gb 02g = 2 gb 04g = 4 gb device family s34ml - 3v spansion slc nand flash memory for embedded valid combinations device family density technology bus width package type temperature range additional ordering options packing type package description s34ml 01g 1 00, 04 tf, bh i a, v, b (2) 00, 01 0, 3 tsop, bga (1) 02g 04g free datasheet http://www.datasheet-pdf.com/
72 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet 11. revision history section description revision 01 (april 16, 2012) initial release revision 02 (may 4, 2012) global removed spansion confidential designation read status enhanced updated text command set updated table: command set read id updated table: read id for supported configurations legacy read id removed section heading: legacy read id valid blocks updated table: valid blocks revision 03 (may 23, 2012) global changed cache read to read cache general description updated text block diagram combined three block diagrams into one addressing updated address cycle map tables mode selection updated table: busy time in read; updated note command set updated table added ?supported in S34ML01G1? column copy back program updated text multiplane copy back program updated text special read for copy back updated text read edc status register updated text read id read id byte 4 description ? S34ML01G1 table: changed number of i/o to spare area size (byte / 512 byte) absolute maximum ratings updated input or output voltage and supply voltage rows program / erase characteristics updated table revision 04 (may 24, 2012) performance updated performance section read id updated read id for supported configurations table modified tables: read id byte 3 description, re ad id byte 4 description ? S34ML01G1, read id byte 4 description ? s34ml02g1 and s34ml04g1, read id byte 5 description ? s34ml02g1 and s34ml04g1 ac test conditions updated table revision 05 (may 31, 2012) global data sheet designation updated from advance information to preliminary distinctive characteristics/performance updated di stinctive characteristics and performance section pin description updated pin description table addressing updated address cycle map ? 1 gb device table updated address cycle map ? 2 gb device table updated address cycle map ? 4 gb device table command set updated command set table revision 06 (july 13, 2012) performance corrected page read/program - sequential access: from 25ns (max) to 25 ns (min) connection diagram corrected figure: 48-pin tsop1 contact x8 device mode selection mode selection table: corrected busy time in read, we# from high to x; corrected notes command set command set table: added onfi, extended read status, and read id2 commands note that all onfi information is in the advanced information designation free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 73 data sheet copy back program updated section multiplane copy back program ? s34ml02g1 and s34ml04g1 updated section read id2 added section read onfi signature added section note that all onfi information is in the advanced information designation read parameter page added section note that all onfi information is in the advanced information designation one-time programmable (otp) entry added section note that all onfi information is in the advanced information designation program/erase characteristics added note to table timing diagrams rearranged section added timing diagrams: multiplane block erase (o nfi 1.0 protocol), multiplane cache program (onfi 1.0 protocol), read id2 operation timing, onfi signature timing, read parameter page timing, read id2 operation timing, otp entry timing updated timing diagrams: page read operat ion (read one page), page read operation intercepted by ce#, page read operation timing wi th ce# don?t care, page program operation, page program operation timing with ce# don?t care, random data input, random data output, multiplane page program, block erase operation (erase one block), reset operation timing, read cache operation timing, cache program, multip lane cache program, read id operation timing note that all onfi information is in the advanced information designation revision 07 (july 23, 2012) command set command set table: changed read onfi signature to ?yes? for supported on S34ML01G1 read parameter page parameter page description table: changed byte 254-255 values valid blocks valid blocks table: removed note 1 and note 3 dc characteristics dc characteristics and operating conditions table: corrected output low voltage test conditions corrected output low current (r/b#) typ and max values revision 08 (august 2, 2012) global note that all onfi information is now in the preliminary designation read parameter page parameter page description table: updated values for bytes 6-7, 108-109, 254-255 physical interface added tsop (2 ce 8 gb) diagram added bga diagram ordering information updated data appendix a added errata revision 09 (august 29, 2012) global removed 8 gb data added x16 i/o bus width data revision 10 (september 6, 2012) connection diagram 48-pin tsop1 contact x8, x16 de vices figure: corrected pinouts 63-vfbga contact, x16 device (balls down, top view) figure: corrected pinouts, removed note command set reorganized section ac characteristics corrected t als min and t ds min revision 11 (october 1, 2012) addressing address cycle map ? 1 gb device: corrected data address cycle map ? 2 gb device: corrected data address cycle map ? 4 gb device: corrected data multiplane program ? s34ml02g1 and s34ml04g1 added text block erase added text section description free datasheet http://www.datasheet-pdf.com/
74 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet multiplane block erase ? s34ml02g1 and s34ml04g1 added text copy back program added text multiplane copy back program ? s34ml02g1 and s34ml04g1 added text multiplane cache program ? s34ml02g1 and s34ml04g1 added text read parameter page parameter page description table: corrected electrical parameters bloc k values for bytes 129-130 and bytes 131-132 corrected vendor block values for bytes 254-255 multiplane page program operation ? s34ml02g1 and s34ml04g1 added note to multiplane page program figure added note to multiplane page prog ram (onfi 1.0 protocol) figure multiplane block erase ? s34ml02g1 and s34ml04g1 added note to multiplane block erase figure updated note to multiplane block erase (onfi 1.0 protocol) figure multiplane copy back program ? s34ml02g1 and s34ml04g1 added note to multiplane copy back program figure multiplane copy back program (onfi 1. 0 protocol) figure: corrected iox values updated note multiplane cache program ? s34ml02g1 and s34ml04g1 added note to multiplane cache program figure multiplane cache program (onfi 1.0 protocol) figure: removed address values from ry/by# changed iox value from f1h to 70h updated note ac characteristics ac characteri stics table: added ce# access time revision 12 (november 2, 2012) global data sheet designation updated from preliminary to full production absolute maximum ratings added note ordering information valid combinations table: added to additional ordering options revision 13 (december 19, 2012) command set added page reprogram command changed readid2 to be ?supported on S34ML01G1? page reprogram moved section added paragraph copy back program added paragraph reset updated paragraph readid2 updated paragraph read parameter page parameter page description table: fixed values of bytes 6-7 and 254-255 fixed description of bytes 129-130 and 131-132 dc characteristics dc characteristics and operating conditions table: power-on reset current (S34ML01G1): removed row operating current: removed i cc1 : t rc = t rc (min); i cc2 : removed cache (S34ML01G1) input leakage current: removed v in = 0 to v cc (max) output leakage current: removed v out = 0 to v cc (max) output high voltage: removed i oh = -100 a, i oh = 100 a, and i oh = 400 a rows output low voltage: removed i ol = -100 a row output low current (r/b#): removed v ol = 0.1v row ac characteristics ac characteristics table: added note page read operation page read operation (read one page) figure: added note read id2 operation timing read id2 operation timing figure: replaced t whr with t r and added r/b# timing signal added note section description free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 75 data sheet bad block management added text bad block management flowchart: updated note revision 14 (february 28, 2013) command set command set table: removed ?nth page? entries page program added paragraph multiplane program ? s34ml02g1 and s34ml04g1 added paragraph page reprogram ? s34ml02g1 and s34ml04g1 added paragraph block erase added paragraph multiplane block erase ? s34ml02g1 and s34ml04g1 added paragraph copy back program added paragraph multiplane copy back program ? s34ml02g1 and s34ml04g1 added paragraph cache program ? s34ml02g1 and s34ml04g1 added paragraph multiplane cache program ? s34ml02g1 and s34ml04g1 added paragraph read parameter page added paragraph electrical characteri stics valid blocks table: updated table ac characteristics ac characteristic s table: corrected min value for t cls and max value for t cea read status cycle timing status / edc read cycle figure: removed note revision 15 (march 7, 2013) ready/busy updated section corrected ready/busy pin electrical application figure revision 16 (august 9, 2013) distinctive characteristics security: removed serial number (unique id) operating temperature: removed commercial and extended temperatures performance updated reliability general description updated section removed bullet: serial number (unique identifier) addressing appended note in all address cycle map tables added text to bus cycle column in all address cycle map tables mode selection updated mode selection table command set command set table: updated acceptable command during busy column changed status of cache program (end) and cache program (start) / (continue) to ?supported on S34ML01G1? page read updated section page program changed sentence ?in addition, pages must be sequentia lly programmed within a block.? to ?pages may be programmed in any order within a block.? multiplane program ? s34ml02g1 and s34ml04g1 changed sentence ?in addition, pages must be programmed sequentially within a block.? to ?pages may be programmed in any order within a block.? page reprogram ? s34ml02g1 and s34ml04g1 corrected page reprogram figure corrected page reprogram with data manipulation figure copy back program updated section read status enhanced ? s34ml02g1 and s34ml04g1 updated section read status register field definition updated status register coding table section description free datasheet http://www.datasheet-pdf.com/
76 spansion ? slc nand flash memory for embedded S34ML01G1_04g1_17 november 22, 2013 data sheet cache program removed s34ml02g1 and s34ml04g1 from heading read id read id bytes: updated description read parameter page parameter page description table: corrected values for bytes 8-9 and 254-255 absolute maximum ratings updated absolute maximum ratings table multiplane page program operation ? s34ml02g1 and s34ml04g1 updated multiplane page program figure updated multiplane page program (onfi 1.0 protocol) copy back read with optional data readout corrected copy back read with optional data readout figure copy back program operation with random data input updated copy back program operation with random data input figure read status register timing remov ed read status enhanced cycle figure read status enhanced timing remo ved read status timing figure read cache updated read cache operation timing figure removed cache timing heading cache program updated cache program figure multiplane cache program ? s34ml02g1 and s34ml04g1 updated multiplane cache program figure updated multiplane cache program (onfi 1.0 protocol) figure read parameter page timing added note to read parameter page timing figure one-time programmable (otp) entry added note stating that the ot p feature in the S34ML01G1 does not have non-volatile protection electrical characteristics absolute maximum ratings table: removed ambient operating temperature (commercial temperature range) and ambient operating temperature (extended temperature range) physical interface updated figures: ts/tsr 48 ? 48-lead plastic thin small outline, 12 x 20 mm, package outline vbm063 ? 63-pin bga, 11 mm x 9 mm package system interface updated read oper ation with ce# don't care figure ordering information updated materials set: h = low halogen to h = lead (pb)-free and low halogen added note to valid combinations table revision 17 (november 22, 2013) distinctive characteristics operat ing temperature: added automotive read id updated section ordering information temperature range: added a, v, b valid combinations temperature range: added a, v, b added note section description free datasheet http://www.datasheet-pdf.com/
november 22, 2013 S34ML01G1_04g1_17 spansion ? slc nand flash memory for embedded 77 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2012-2013 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse ? , ornand ? and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. other names used are for informational purposes only and may be trademarks of their respective owners. free datasheet http://www.datasheet-pdf.com/

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